mirror of
https://github.com/TomHarte/CLK.git
synced 2024-11-26 23:52:26 +00:00
Improves test machine and incorporates a first test of LINK.
This commit is contained in:
Thomas Harte
parent
ccfe1b13cb
commit
6b996ae57d
@ -24,8 +24,6 @@ using Flag = CPU::MC68000::Flag;
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class RAM68000: public CPU::MC68000::BusHandler {
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public:
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RAM68000() : m68000_(*this) {
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ram_.resize(256*1024);
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// Setup the /RESET vector.
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ram_[0] = 0;
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ram_[1] = 0x206; // Supervisor stack pointer.
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@ -37,23 +35,37 @@ class RAM68000: public CPU::MC68000::BusHandler {
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memcpy(&ram_[0x1000 >> 1], program.data(), program.size() * sizeof(uint16_t));
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}
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void set_initial_stack_pointer(uint32_t sp) {
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ram_[0] = sp >> 16;
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ram_[1] = sp & 0xffff;
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}
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void will_perform(uint32_t address, uint16_t opcode) {
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--instructions_remaining_;
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}
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void run_for_instructions(int count) {
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instructions_remaining_ = count;
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if(!has_run_) ++instructions_remaining_;
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while(instructions_remaining_) {
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run_for(HalfCycles(2));
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}
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}
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void run_for(HalfCycles cycles) {
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// If the 68000 hasn't run yet, build in the necessary
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// cycles to finish the reset program, and set the stored state.
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if(!has_run_) {
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has_run_ = true;
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m68000_.run_for(HalfCycles(76));
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duration_ -= HalfCycles(76);
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}
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m68000_.run_for(cycles);
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}
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uint16_t *ram_at(uint32_t address) {
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return &ram_[address >> 1];
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return &ram_[(address >> 1) % ram_.size()];
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}
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HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int is_supervisor) {
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@ -69,16 +81,16 @@ class RAM68000: public CPU::MC68000::BusHandler {
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default: break;
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case Microcycle::SelectWord | Microcycle::Read:
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cycle.value->full = ram_[word_address];
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cycle.value->full = ram_[word_address % ram_.size()];
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break;
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case Microcycle::SelectByte | Microcycle::Read:
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cycle.value->halves.low = ram_[word_address] >> cycle.byte_shift();
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cycle.value->halves.low = ram_[word_address % ram_.size()] >> cycle.byte_shift();
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break;
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case Microcycle::SelectWord:
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ram_[word_address] = cycle.value->full;
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ram_[word_address % ram_.size()] = cycle.value->full;
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break;
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case Microcycle::SelectByte:
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ram_[word_address] = uint16_t(
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ram_[word_address % ram_.size()] = uint16_t(
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(cycle.value->halves.low << cycle.byte_shift()) |
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(ram_[word_address] & cycle.untouched_byte_mask())
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);
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@ -103,14 +115,15 @@ class RAM68000: public CPU::MC68000::BusHandler {
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}
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int get_cycle_count() {
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return (duration_.as_int() >> 1) - 26; // TODO: 26 doesn't sound right for RESET. Check.
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return duration_.as_int() >> 1;
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}
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private:
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CPU::MC68000::Processor<RAM68000, true, true> m68000_;
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std::vector<uint16_t> ram_;
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std::array<uint16_t, 256*1024> ram_;
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int instructions_remaining_;
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HalfCycles duration_;
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bool has_run_ = false;
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};
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class CPU::MC68000::ProcessorStorageTests {
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@ -248,17 +261,14 @@ class CPU::MC68000::ProcessorStorageTests {
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/* Next instruction would be at 0x406 */
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});
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auto state = _machine->get_processor_state();
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state.supervisor_stack_pointer = 0x1000;
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_machine->set_processor_state(state);
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_machine->set_initial_stack_pointer(0x1000);
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_machine->run_for_instructions(4);
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state = _machine->get_processor_state();
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const auto state = _machine->get_processor_state();
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XCTAssert(state.supervisor_stack_pointer == 0x1000 - 6, @"Exception information should have been pushed to stack.");
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const uint16_t *stack_top = _machine->ram_at(state.supervisor_stack_pointer);
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const uint16_t *const stack_top = _machine->ram_at(state.supervisor_stack_pointer);
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XCTAssert(stack_top[1] == 0x0000 && stack_top[2] == 0x1006, @"Return address should point to instruction after DIVU.");
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}
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@ -543,7 +553,7 @@ class CPU::MC68000::ProcessorStorageTests {
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state.data[1] = 0x1234567a;
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state.data[2] = 0xf745ff78;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssert(state.status & Flag::Carry);
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@ -560,7 +570,7 @@ class CPU::MC68000::ProcessorStorageTests {
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state.data[2] = 0x12345600;
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state.status = Flag::Zero;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssert(state.status & Flag::Zero);
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@ -577,7 +587,7 @@ class CPU::MC68000::ProcessorStorageTests {
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state.data[2] = 0x12345654;
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state.status = Flag::Zero;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssert(state.status & Flag::Negative);
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@ -594,7 +604,7 @@ class CPU::MC68000::ProcessorStorageTests {
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state.data[2] = 0x12345654;
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state.status = Flag::Extend;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssert(state.status & Flag::Carry);
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@ -611,7 +621,7 @@ class CPU::MC68000::ProcessorStorageTests {
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state.data[2] = 0x1234563e;
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state.status = Flag::Extend;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssert(state.status & Flag::Overflow);
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@ -631,7 +641,7 @@ class CPU::MC68000::ProcessorStorageTests {
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state.address[2] = 0x4001;
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state.status = Flag::Extend;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssert(state.status & Flag::Carry);
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@ -652,7 +662,7 @@ class CPU::MC68000::ProcessorStorageTests {
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state.address[1] = 0x3002;
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state.status = Flag::Extend;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssert(state.status & Flag::Carry);
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@ -670,7 +680,7 @@ class CPU::MC68000::ProcessorStorageTests {
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auto state = _machine->get_processor_state();
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state.data[2] = 0x9ae;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Negative | Flag::Extend);
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@ -684,7 +694,7 @@ class CPU::MC68000::ProcessorStorageTests {
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auto state = _machine->get_processor_state();
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state.data[2] = 0x82;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Overflow | Flag::Carry | Flag::Extend);
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@ -699,7 +709,7 @@ class CPU::MC68000::ProcessorStorageTests {
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state.data[2] = 0x82;
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*_machine->ram_at(0x3000) = 0x8200;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Overflow | Flag::Carry | Flag::Extend);
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@ -714,7 +724,7 @@ class CPU::MC68000::ProcessorStorageTests {
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auto state = _machine->get_processor_state();
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state.data[2] = 0x3e8;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.data[2], 0x7D0);
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@ -731,7 +741,7 @@ class CPU::MC68000::ProcessorStorageTests {
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*_machine->ram_at(0x2002) = 0x9400;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.data[2], 0xb2d05e00);
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@ -751,7 +761,7 @@ class CPU::MC68000::ProcessorStorageTests {
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*_machine->ram_at(0x2002) = 0xffff;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.data[2], 0xFFFF0000);
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@ -773,7 +783,7 @@ class CPU::MC68000::ProcessorStorageTests {
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state.data[2] = 0x012557ac;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.data[1], 0xfe35aab0);
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@ -792,7 +802,7 @@ class CPU::MC68000::ProcessorStorageTests {
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state.status = Flag::ConditionCodes;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.address[2], 0xc0780195);
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@ -808,7 +818,7 @@ class CPU::MC68000::ProcessorStorageTests {
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state.status = Flag::ConditionCodes;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.address[2], 0xae440195);
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@ -824,7 +834,7 @@ class CPU::MC68000::ProcessorStorageTests {
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state.status = Flag::ConditionCodes;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.address[2], 0xae43a195);
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@ -839,7 +849,7 @@ class CPU::MC68000::ProcessorStorageTests {
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state.status = Flag::ConditionCodes;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.address[2], 0xfffff000);
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@ -857,7 +867,7 @@ class CPU::MC68000::ProcessorStorageTests {
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*_machine->ram_at(0x2002) = 0;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.address[2], 0x70022000);
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@ -877,7 +887,7 @@ class CPU::MC68000::ProcessorStorageTests {
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state.data[2] = 1;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.data[2], d2Output);
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@ -1057,7 +1067,7 @@ class CPU::MC68000::ProcessorStorageTests {
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state.status = Flag::ConditionCodes;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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}
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- (void)performDIVSOverflowTestDivisor:(uint16_t)divisor {
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@ -1188,18 +1198,37 @@ class CPU::MC68000::ProcessorStorageTests {
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- (void)testDIVSException {
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// DIVS.W #0, D1
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auto state = _machine->get_processor_state();
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state.supervisor_stack_pointer = 0;
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_machine->set_processor_state(state);
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_machine->set_initial_stack_pointer(0);
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[self performDivide:0x0 a1:0x1fffffff];
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state = _machine->get_processor_state();
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const auto state = _machine->get_processor_state();
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XCTAssertEqual(state.data[1], 0x1fffffff);
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XCTAssertEqual(state.supervisor_stack_pointer, 0xfffffffa);
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XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
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// XCTAssertEqual(42, _machine->get_cycle_count());
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}
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// MARK: LINK
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- (void)testLINKA15 {
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_machine->set_program({
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0x4e51, 0x0005 // LINK a1, #5
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});
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auto state = _machine->get_processor_state();
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state.address[1] = 0x11111111;
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_machine->set_initial_stack_pointer(0x22222222);
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_machine->set_processor_state(state);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.address[1], 0x2222221e);
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XCTAssertEqual(state.supervisor_stack_pointer, 0x22222223);
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XCTAssertEqual(*_machine->ram_at(0x2222221e), 0x1111);
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XCTAssertEqual(*_machine->ram_at(0x22222220), 0x1111);
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XCTAssertEqual(16, _machine->get_cycle_count());
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}
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// MARK: MOVE from SR
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- (void)testMoveFromSR {
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@ -1210,7 +1239,7 @@ class CPU::MC68000::ProcessorStorageTests {
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state.status = 0x271f;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.data[1], 0x271f);
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@ -1228,7 +1257,7 @@ class CPU::MC68000::ProcessorStorageTests {
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state.address[1] = 0x12348756;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.address[1], 0);
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@ -1246,7 +1275,7 @@ class CPU::MC68000::ProcessorStorageTests {
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state.status = ccr;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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}
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- (void)performMULConstant:(uint16_t)constant d2:(uint32_t)d2 {
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@ -1258,7 +1287,7 @@ class CPU::MC68000::ProcessorStorageTests {
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state.status = Flag::Carry | Flag::Extend | Flag::Overflow;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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}
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- (void)testMULS {
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@ -1320,7 +1349,7 @@ class CPU::MC68000::ProcessorStorageTests {
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state.status = Flag::Extend;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.data[0], 0x12345600);
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@ -1336,7 +1365,7 @@ class CPU::MC68000::ProcessorStorageTests {
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state.status = Flag::Extend;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.data[0], 0x123456ff);
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@ -1352,7 +1381,7 @@ class CPU::MC68000::ProcessorStorageTests {
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state.status = Flag::ConditionCodes;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.data[0], 0x123456ff);
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@ -1369,7 +1398,7 @@ class CPU::MC68000::ProcessorStorageTests {
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state.status = Flag::Extend;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(*_machine->ram_at(0x3002), 0xff00);
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@ -1386,7 +1415,7 @@ class CPU::MC68000::ProcessorStorageTests {
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state.status = Flag::ConditionCodes;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(*_machine->ram_at(0x3002), 0x0000);
|
||||
@ -1403,7 +1432,7 @@ class CPU::MC68000::ProcessorStorageTests {
|
||||
state.data[1] = 0x12348756;
|
||||
|
||||
_machine->set_processor_state(state);
|
||||
_machine->run_for_instructions(2);
|
||||
_machine->run_for_instructions(1);
|
||||
|
||||
state = _machine->get_processor_state();
|
||||
XCTAssertEqual(state.data[1], 0x87561234);
|
||||
@ -1424,7 +1453,7 @@ class CPU::MC68000::ProcessorStorageTests {
|
||||
*_machine->ram_at(0xfffe) = 0x4e71;
|
||||
|
||||
_machine->set_processor_state(state);
|
||||
_machine->run_for_instructions(2);
|
||||
_machine->run_for_instructions(1);
|
||||
|
||||
state = _machine->get_processor_state();
|
||||
XCTAssertEqual(state.status, 0x2700);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user