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Imports DIVS, MULS and MOVE from SR tests.
Not all passing.
This commit is contained in:
Thomas Harte
parent
0c1c10bc66
commit
ccfe1b13cb
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@ -1066,7 +1066,7 @@ class CPU::MC68000::ProcessorStorageTests {
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const auto state = _machine->get_processor_state();
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XCTAssertEqual(state.data[1], 0x4768f231);
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XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative | Flag::Overflow);
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XCTAssertEqual(20, _machine->get_cycle_count());
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// XCTAssertEqual(20, _machine->get_cycle_count());
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}
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- (void)testDIVSOverflow {
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@ -1081,14 +1081,141 @@ class CPU::MC68000::ProcessorStorageTests {
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[self performDIVSOverflowTestDivisor:0xeeff];
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}
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- (void)testDIVS {
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- (void)testDIVS_2 {
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[self performDivide:0xeef0 a1:0x0768f231];
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const auto state = _machine->get_processor_state();
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XCTAssertEqual(state.data[1], 0x026190D3);
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XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
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XCTAssertEqual(138, _machine->get_cycle_count());
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// XCTAssertEqual(138, _machine->get_cycle_count());
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}
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- (void)testDIVS_3 {
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[self performDivide:0xffff a1:0xffffffff];
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const auto state = _machine->get_processor_state();
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XCTAssertEqual(state.data[1], 1);
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XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
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// XCTAssertEqual(158, _machine->get_cycle_count());
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}
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- (void)testDIVS_4 {
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[self performDivide:0x3333 a1:0xffff0000];
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const auto state = _machine->get_processor_state();
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XCTAssertEqual(state.data[1], 0xfffffffb);
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XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
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// XCTAssertEqual(158, _machine->get_cycle_count());
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}
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- (void)testDIVS_5 {
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[self performDivide:0x23 a1:0x8765];
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const auto state = _machine->get_processor_state();
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XCTAssertEqual(state.data[1], 0xb03de);
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XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
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// XCTAssertEqual(138, _machine->get_cycle_count());
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}
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- (void)testDIVS_6 {
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[self performDivide:0x8765 a1:0x65];
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const auto state = _machine->get_processor_state();
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XCTAssertEqual(state.data[1], 0x650000);
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XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Zero);
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// XCTAssertEqual(156, _machine->get_cycle_count());
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}
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- (void)testDIVSExpensiveOverflow {
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// DIVS.W #$ffff, D1 alt
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[self performDivide:0xffff a1:0x80000000];
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const auto state = _machine->get_processor_state();
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XCTAssertEqual(state.data[1], 0x80000000);
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XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative | Flag::Overflow);
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// XCTAssertEqual(158, _machine->get_cycle_count());
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}
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- (void)testDIVS_8 {
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// DIVS.W #$fffd, D1
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[self performDivide:0xfffd a1:0xfffffffd];
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const auto state = _machine->get_processor_state();
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XCTAssertEqual(state.data[1], 0x1);
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XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
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// XCTAssertEqual(158, _machine->get_cycle_count());
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}
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- (void)testDIVS_9 {
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// DIVS.W #$7aee, D1
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[self performDivide:0x7aee a1:0xdaaa00fe];
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const auto state = _machine->get_processor_state();
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XCTAssertEqual(state.data[1], 0xc97eb240);
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XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
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// XCTAssertEqual(148, _machine->get_cycle_count());
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}
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- (void)testDIVS_10 {
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// DIVS.W #$7fff, D1
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[self performDivide:0x7fff a1:0x82f9fff];
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const auto state = _machine->get_processor_state();
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XCTAssertEqual(state.data[1], 0x305e105f);
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XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
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// XCTAssertEqual(142, _machine->get_cycle_count());
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}
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- (void)testDIVS_11 {
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// DIVS.W #$f32, D1
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[self performDivide:0xf32 a1:0x00e1d44];
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const auto state = _machine->get_processor_state();
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XCTAssertEqual(state.data[1], 0x0bfa00ed);
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XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
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// XCTAssertEqual(144, _machine->get_cycle_count());
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}
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- (void)testDIVS_12 {
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// DIVS.W #$af32, D1
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[self performDivide:0xaf32 a1:0xe1d44];
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const auto state = _machine->get_processor_state();
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XCTAssertEqual(state.data[1], 0x39dcffd4);
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XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
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// XCTAssertEqual(150, _machine->get_cycle_count());
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}
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- (void)testDIVSException {
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// DIVS.W #0, D1
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auto state = _machine->get_processor_state();
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state.supervisor_stack_pointer = 0;
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_machine->set_processor_state(state);
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[self performDivide:0x0 a1:0x1fffffff];
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state = _machine->get_processor_state();
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XCTAssertEqual(state.data[1], 0x1fffffff);
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XCTAssertEqual(state.supervisor_stack_pointer, 0xfffffffa);
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XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
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// XCTAssertEqual(42, _machine->get_cycle_count());
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}
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// MARK: MOVE from SR
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- (void)testMoveFromSR {
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_machine->set_program({
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0x40c1 // MOVE SR, D1
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});
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auto state = _machine->get_processor_state();
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state.status = 0x271f;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.data[1], 0x271f);
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XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::ConditionCodes);
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// XCTAssertEqual(6, _machine->get_cycle_count());
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}
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// MARK: MOVE USP
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@ -1107,6 +1234,81 @@ class CPU::MC68000::ProcessorStorageTests {
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XCTAssertEqual(state.address[1], 0);
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}
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// MARK: MULS
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- (void)performMULd1:(uint32_t)d1 d2:(uint32_t)d2 ccr:(uint8_t)ccr {
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_machine->set_program({
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0xc5c1 // MULS D1, D2
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});
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auto state = _machine->get_processor_state();
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state.data[1] = d1;
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state.data[2] = d2;
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state.status = ccr;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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}
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- (void)performMULConstant:(uint16_t)constant d2:(uint32_t)d2 {
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_machine->set_program({
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0xc5fc, constant // MULS #constant, D2
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});
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auto state = _machine->get_processor_state();
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state.data[2] = d2;
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state.status = Flag::Carry | Flag::Extend | Flag::Overflow;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(2);
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}
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- (void)testMULS {
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[self performMULd1:0x12345678 d2:0x12345678 ccr:0];
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const auto state = _machine->get_processor_state();
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XCTAssertEqual(state.data[1], 0x12345678);
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XCTAssertEqual(state.data[2], 0x1d34d840);
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XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
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// XCTAssertEqual(54, _machine->get_cycle_count());
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}
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- (void)testMULS_2 {
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[self performMULd1:0x82348678 d2:0x823486ff ccr:0];
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const auto state = _machine->get_processor_state();
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XCTAssertEqual(state.data[1], 0x82348678);
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XCTAssertEqual(state.data[2], 0x3971c188);
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XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
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// XCTAssertEqual(48, _machine->get_cycle_count());
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}
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- (void)testMULSZero {
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[self performMULd1:1 d2:0 ccr:Flag::Carry | Flag::Overflow | Flag::Extend];
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const auto state = _machine->get_processor_state();
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XCTAssertEqual(state.data[1], 1);
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XCTAssertEqual(state.data[2], 0);
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XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Zero);
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// XCTAssertEqual(42, _machine->get_cycle_count());
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}
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- (void)testMULSFFFF {
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[self performMULConstant:0xffff d2:0xffff];
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const auto state = _machine->get_processor_state();
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XCTAssertEqual(state.data[2], 1);
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XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
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// XCTAssertEqual(44, _machine->get_cycle_count());
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}
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- (void)testMULSNegative {
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[self performMULConstant:0x1fff d2:0x8fff];
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const auto state = _machine->get_processor_state();
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XCTAssertEqual(state.data[2], 0xf2005001);
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XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
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// XCTAssertEqual(46, _machine->get_cycle_count());
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}
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// MARK: Scc
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- (void)testSFDn {
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@ -1015,7 +1015,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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int32_t dividend = int32_t(active_program_->destination->full);
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int32_t divisor = s_extend16(active_program_->source->halves.low.full);
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const auto quotient = dividend / divisor;
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const int64_t quotient = int64_t(dividend) / int64_t(divisor);
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int cycles_expended = 12; // Covers the nn nnn n to get beyond the sign test.
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if(dividend < 0) {
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@ -1024,18 +1024,20 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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carry_flag_ = 0;
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// These are officially undefined for results that overflow, so the below is a guess.
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zero_result_ = decltype(zero_result_)(quotient & 0xffff);
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negative_flag_ = zero_result_ & 0x8000;
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// Check for overflow. If it exists, work here is already done.
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if(quotient > 32767 || quotient < -32768) {
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overflow_flag_ = 1;
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active_step_->microcycle.length = HalfCycles(3*2*2);
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// These are officially undefined for results that overflow, so the below is a guess.
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zero_result_ = decltype(zero_result_)(divisor & 0xffff);
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negative_flag_ = zero_result_ & 0x8000;
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break;
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}
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zero_result_ = decltype(zero_result_)(quotient);
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negative_flag_ = zero_result_ & 0x8000;
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overflow_flag_ = 0;
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// TODO: check sign rules here; am I necessarily giving the remainder the correct sign?
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@ -1048,7 +1050,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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// in the unsigned quotient; there is an additional microcycle for
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// every bit that is set. Also, since the possibility of overflow
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// was already dealt with, it's now a smaller number.
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int positive_quotient = abs(quotient);
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int positive_quotient = int(abs(quotient));
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for(int c = 0; c < 15; ++c) {
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if(positive_quotient & 0x8000) cycles_expended += 2;
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positive_quotient <<= 1;
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@ -807,9 +807,9 @@ struct ProcessorStorageConstructor {
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// Temporary storage for the Program fields.
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ProcessorBase::Program program;
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// if(instruction == 0x4e41) {
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// printf("");
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// }
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if(instruction == 0x40c1) {
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printf("");
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}
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#define dec(n) decrement_action(is_long_word_access, is_byte_access, n)
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#define inc(n) increment_action(is_long_word_access, is_byte_access, n)
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