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Fixes predecrementing MOVEM to leave the proper address in the relevant register.

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This commit is contained in:
Thomas Harte 2019-04-22 15:41:09 -04:00
parent 55073b0a52
commit 6d6046757d
2 changed files with 7 additions and 2 deletions
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5
OSBindings/Mac/Clock SignalTests/QLTests.mm
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@ -11,6 +11,9 @@
#include <array>
#include <cassert>
#include <iostream>
#include <fstream>
#include "68000.hpp"
#include "CSROMFetcher.hpp"
@ -107,6 +110,8 @@ class QL: public CPU::MC68000::BusHandler {
std::unique_ptr<QL> _machine;
}
std::streambuf *coutbuf;
- (void)setUp {
const auto roms = CSROMFetcher()("SinclairQL", {"js.rom"});
_machine.reset(new QL(*roms[0]));

4
Processors/68000/Implementation/68000Implementation.hpp
View File

@ -52,7 +52,7 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
// no instruction was ongoing. Either way, do a standard instruction operation.
// TODO: unless an interrupt is pending, or the trap flag is set.
static bool should_log = false;
// static bool should_log = false;
// should_log |= program_counter_.full >= 0x4F54 && program_counter_.full <= 0x4F84;
// if(should_log) {
@ -654,7 +654,7 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
offset = 15;
start_address -= 2;
write_address_sequence_long(dec_action, 2);
movem_final_address_ = start_address;
movem_final_address_ = start_address + 2;
} else {
write_address_sequence_long(inc_action, 0);
}