Immediately runs afoul of a read/write difference in the specs between 8/16-bit mode that suggests maybe this isn't a good structure.

Perhaps generators of some sort?

Processors/65816/Implementation/65816Storage.cpp

@@ -62,6 +62,19 @@ ProcessorStorage::ProcessorStorage() {
 			OperationMoveToNextProgram
 		});
 
+	// 1d. Absolute read-modify-write.
+//	const auto absolute_rmw =
+//		install_ops({
+//			CycleFetchIncrementPC,			// OpCode.
+//			CycleFetchIncrementPC,			// AAL.
+//			CycleFetchIncrementPC,			// AAH.
+//			CycleFetchIncrementData,		// Data low.
+//			OperationSkipIf8,				// (don't do the next fetch if in emulation mode)
+//			CycleFetchIncrementData,		// Data high.
+//			OperationPerform,				// (whatever the operation is)
+//			OperationMoveToNextProgram
+//		});
+
 	// Install the instructions.
 #define op set_instruction
 	/* 0x00 BRK s */

Processors/65816/Implementation/65816Storage.hpp

@@ -23,6 +23,8 @@ class ProcessorStorage {
 			CycleFetchIncrementData,
 			/// Stores a byte to the data address from the data buffer and increments the data address.
 			CycleStoreIncrementData,
+			/// Decrements the data address and writes a byte to it.
+			CycleDecrementStoreData,
 
 			/// Pushes a single byte from the data buffer to the stack.
 			CyclePush,