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Resolve final branch test: aa() applies.
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@ -120,8 +120,9 @@ enum class Operation: uint8_t {
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/// Branch conditional.
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///
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/// aa() determines whether the branch has a relative or absolute target.
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/// lk() determines whether to update the link register.
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/// bd() supplies a relative displacment.
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/// bd() supplies a relative displacment or absolute address.
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/// bi() specifies which CR bit to use as a condition; cf. the Condition enum.
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/// bo() provides other branch options and a branch prediction hint as per (BranchOptions enum << 1) | hint.
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///
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@ -131,7 +132,7 @@ enum class Operation: uint8_t {
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/// Branch conditional to count register.
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///
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/// bi(), bo() and lk() are as per bcx.
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/// aa(), bi(), bo() and lk() are as per bcx.
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///
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/// On the MPC601, anything that decrements the count register will use the non-decremented
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/// version as the branch target. Other processors will use the decremented version.
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@ -139,7 +140,7 @@ enum class Operation: uint8_t {
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/// Branch conditional to link register.
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///
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/// bi(), bo() and lk() are as per bcx.
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/// aa(), bi(), bo() and lk() are as per bcx.
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bclrx,
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cmp, cmpi, cmpl, cmpli,
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@ -116,14 +116,14 @@ using namespace InstructionSet::PowerPC;
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break;
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case Operation::bcx: {
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// if(instruction.aa()) {
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// baseOperation = [baseOperation stringByAppendingString:@"a"];
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// } else {
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//
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// }
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uint32_t decoded_destination;
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if(instruction.aa()) {
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decoded_destination = instruction.bd();
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} else {
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decoded_destination = instruction.bd() + address;
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}
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const uint32_t destination = uint32_t(std::strtol([[columns lastObject] UTF8String], 0, 16));
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const uint32_t decoded_destination = instruction.bd() + address;
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XCTAssertEqual(decoded_destination, destination);
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} break;
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@ -136,6 +136,9 @@ using namespace InstructionSet::PowerPC;
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if(instruction.lk()) {
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baseOperation = [baseOperation stringByAppendingString:@"l"];
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}
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if(instruction.aa()) {
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baseOperation = [baseOperation stringByAppendingString:@"a"];
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}
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if(instruction.branch_prediction_hint()) {
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baseOperation = [baseOperation stringByAppendingString:@"+"];
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}
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