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Start removing 68000-specific timing calculations.
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@ -49,8 +49,11 @@ template <Model model, typename BusHandler> class Executor {
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// Flow control.
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// Flow control.
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void consume_cycles(int) {}
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void consume_cycles(int) {}
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void raise_exception(int, bool use_current_instruction_pc = true);
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template <bool use_current_instruction_pc = true> void raise_exception(int);
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void did_update_status();
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void did_update_status();
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template <typename IntT> void did_mulu(IntT) {}
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template <typename IntT> void did_muls(IntT) {}
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template <typename IntT> void complete_bcc(bool matched_condition, IntT offset);
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template <typename IntT> void complete_bcc(bool matched_condition, IntT offset);
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void complete_dbcc(bool matched_condition, bool overflowed, int16_t offset);
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void complete_dbcc(bool matched_condition, bool overflowed, int16_t offset);
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@ -332,7 +332,8 @@ void Executor<model, BusHandler>::set_state(const Registers &state) {
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// MARK: - Flow Control.
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// MARK: - Flow Control.
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template <Model model, typename BusHandler>
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template <Model model, typename BusHandler>
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void Executor<model, BusHandler>::raise_exception(int index, bool use_current_instruction_pc) {
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template <bool use_current_instruction_pc>
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void Executor<model, BusHandler>::raise_exception(int index) {
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const uint32_t address = index << 2;
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const uint32_t address = index << 2;
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// Grab the status to store, then switch into supervisor mode.
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// Grab the status to store, then switch into supervisor mode.
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@ -492,35 +492,22 @@ template <
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Multiplications.
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Multiplications.
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*/
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*/
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case Operation::MULU: {
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case Operation::MULU:
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dest.l = dest.w * src.w;
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dest.l = dest.w * src.w;
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status.carry_flag_ = status.overflow_flag_ = 0;
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status.carry_flag_ = status.overflow_flag_ = 0;
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status.zero_result_ = dest.l;
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status.zero_result_ = dest.l;
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status.negative_flag_ = status.zero_result_ & 0x80000000;
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status.negative_flag_ = status.zero_result_ & 0x80000000;
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flow_controller.did_mulu(src.w);
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break;
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int number_of_ones = src.w;
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case Operation::MULS:
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convert_to_bit_count_16(number_of_ones);
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// Time taken = 38 cycles + 2 cycles for every 1 in the source.
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flow_controller.consume_cycles(2 * number_of_ones + 34);
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} break;
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case Operation::MULS: {
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dest.l =
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dest.l =
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u_extend16(dest.w) * u_extend16(src.w);
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u_extend16(dest.w) * u_extend16(src.w);
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status.carry_flag_ = status.overflow_flag_ = 0;
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status.carry_flag_ = status.overflow_flag_ = 0;
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status.zero_result_ = dest.l;
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status.zero_result_ = dest.l;
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status.negative_flag_ = status.zero_result_ & 0x80000000;
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status.negative_flag_ = status.zero_result_ & 0x80000000;
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flow_controller.did_muls(src.w);
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// Find the number of 01 or 10 pairs in the 17-bit number
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break;
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// formed by the source value with a 0 suffix.
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int number_of_pairs = src.w;
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number_of_pairs = (number_of_pairs ^ (number_of_pairs << 1)) & 0xffff;
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convert_to_bit_count_16(number_of_pairs);
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// Time taken = 38 cycles + 2 cycles per 1 in the source.
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flow_controller.consume_cycles(2 * number_of_pairs + 34);
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} break;
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/*
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/*
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Divisions.
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Divisions.
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@ -651,12 +638,12 @@ template <
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// TRAP, which is a nicer form of ILLEGAL.
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// TRAP, which is a nicer form of ILLEGAL.
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case Operation::TRAP:
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case Operation::TRAP:
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flow_controller.raise_exception(src.l + 32, false);
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flow_controller.template raise_exception<false>(src.l + 32);
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break;
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break;
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case Operation::TRAPV: {
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case Operation::TRAPV: {
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if(status.overflow_flag_) {
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if(status.overflow_flag_) {
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flow_controller.raise_exception(7, false);
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flow_controller.template raise_exception<false>(7);
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}
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}
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} break;
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} break;
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@ -682,7 +669,7 @@ template <
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} else {
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} else {
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flow_controller.consume_cycles(12);
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flow_controller.consume_cycles(12);
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}
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}
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flow_controller.raise_exception(6, false);
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flow_controller.template raise_exception<false>(6);
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}
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}
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} break;
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} break;
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@ -157,7 +157,8 @@ static constexpr uint8_t StoreOp2 = (1 << 3);
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/*!
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/*!
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Provides a bitfield with a value in the range 0–15 indicating which of the provided operation's
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Provides a bitfield with a value in the range 0–15 indicating which of the provided operation's
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operands are accessed via standard fetch and store cycles.
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operands are accessed via standard fetch and store cycles; the bitfield is composted of
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[Fetch/Store]Op[1/2] as defined above.
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Unusual bus sequences, such as TAS or MOVEM, are not described here.
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Unusual bus sequences, such as TAS or MOVEM, are not described here.
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*/
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*/
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