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Add a graceful end for JAM.

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This commit is contained in:
Thomas Harte 2024-07-26 21:45:03 -04:00
parent 59e1a5e5f6
commit 76ca607021
1 changed files with 11 additions and 0 deletions
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11
OSBindings/Mac/Clock SignalTests/65816ComparativeTests.mm
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@ -29,6 +29,16 @@ struct BusHandler: public CPU::MOS6502Esque::BusHandlerT<type> {
std::unordered_map<AddressType, uint8_t> inventions; std::unordered_map<AddressType, uint8_t> inventions;
Cycles perform_bus_operation(CPU::MOS6502Esque::BusOperation operation, AddressType address, uint8_t *value) { Cycles perform_bus_operation(CPU::MOS6502Esque::BusOperation operation, AddressType address, uint8_t *value) {
// Check for a JAM; if one is found then record just five more bus cycles, arbitrarily.
if(jam_count) {
--jam_count;
if(!jam_count) {
throw StopException();
}
} else if(processor.is_jammed()) {
jam_count = 5;
}
// Record the basics of the operation. // Record the basics of the operation.
auto &cycle = cycles.emplace_back(); auto &cycle = cycles.emplace_back();
cycle.operation = operation; cycle.operation = operation;
@ -110,6 +120,7 @@ struct BusHandler: public CPU::MOS6502Esque::BusHandlerT<type> {
int pc_overshoot = 0; int pc_overshoot = 0;
std::optional<AddressType> initial_pc; std::optional<AddressType> initial_pc;
bool allow_pc_repetition = false; bool allow_pc_repetition = false;
int jam_count = 0;
struct Cycle { struct Cycle {
CPU::MOS6502Esque::BusOperation operation; CPU::MOS6502Esque::BusOperation operation;