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These are likely to be useful outside of the decoder.

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This commit is contained in:
Thomas Harte 2022-03-21 10:41:17 -04:00
parent 0b6828c895
commit 77bdaf3c78
2 changed files with 16 additions and 16 deletions
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8
InstructionSets/PowerPC/Decoder.cpp
View File

@ -36,11 +36,11 @@ Instruction Decoder::decode(uint32_t opcode) {
#define BindSupervisor(mask, operation) case mask: return Instruction(Operation::operation, opcode, true); #define BindSupervisor(mask, operation) case mask: return Instruction(Operation::operation, opcode, true);
#define BindConditional(condition, mask, operation) \ #define BindConditional(condition, mask, operation) \
case mask: \ case mask: \
if(condition()) return Instruction(Operation::operation, opcode); \ if(condition(model_)) return Instruction(Operation::operation, opcode); \
return Instruction(opcode); return Instruction(opcode);
#define BindSupervisorConditional(condition, mask, operation) \ #define BindSupervisorConditional(condition, mask, operation) \
case mask: \ case mask: \
if(condition()) return Instruction(Operation::operation, opcode, true); \ if(condition(model_)) return Instruction(Operation::operation, opcode, true); \
return Instruction(opcode); return Instruction(opcode);
#define Six(x) (unsigned(x) << 26) #define Six(x) (unsigned(x) << 26)
@ -320,7 +320,7 @@ Instruction Decoder::decode(uint32_t opcode) {
switch(opcode & 0b111111'00'00000000'000'111111111'1){ switch(opcode & 0b111111'00'00000000'000'111111111'1){
case 0b011111'00'00000000'00000'0010010110'1: return Instruction(Operation::stwcx_, opcode); case 0b011111'00'00000000'00000'0010010110'1: return Instruction(Operation::stwcx_, opcode);
case 0b011111'00'00000000'00000'0011010110'1: case 0b011111'00'00000000'00000'0011010110'1:
if(is64bit()) return Instruction(Operation::stdcx_, opcode); if(is64bit(model_)) return Instruction(Operation::stdcx_, opcode);
return Instruction(opcode); return Instruction(opcode);
} }
@ -328,7 +328,7 @@ Instruction Decoder::decode(uint32_t opcode) {
switch(opcode & 0b111111'00'00000000'00000000'000000'11){ switch(opcode & 0b111111'00'00000000'00000000'000000'11){
case 0b111110'00'00000000'00000000'000000'00: return Instruction(Operation::std, opcode); case 0b111110'00'00000000'00000000'000000'00: return Instruction(Operation::std, opcode);
case 0b111110'00'00000000'00000000'000000'01: case 0b111110'00'00000000'00000000'000000'01:
if(is64bit()) return Instruction(Operation::stdu, opcode); if(is64bit(model_)) return Instruction(Operation::stdu, opcode);
return Instruction(opcode); return Instruction(opcode);
} }

24
InstructionSets/PowerPC/Decoder.hpp
View File

@ -23,6 +23,18 @@ enum class Model {
MPC620, MPC620,
}; };
constexpr bool is64bit(Model model) {
return model == Model::MPC620;
}
constexpr bool is32bit(Model model) {
return !is64bit(model);
}
constexpr bool is601(Model model) {
return model == Model::MPC601;
}
/*! /*!
Implements PowerPC instruction decoding. Implements PowerPC instruction decoding.
@ -36,18 +48,6 @@ struct Decoder {
private: private:
Model model_; Model model_;
bool is64bit() const {
return model_ == Model::MPC620;
}
bool is32bit() const {
return !is64bit();
}
bool is601() const {
return model_ == Model::MPC601;
}
}; };
} }