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https://github.com/TomHarte/CLK.git
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Implemented EX DE, HL and shuffled to allow instruction pages.
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Thomas Harte
parent
add02a7897
commit
7b234078ae
@ -104,6 +104,11 @@ struct MicroOp {
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TestP,
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TestM,
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Add16,
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ExDEHL,
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SetInstructionPage,
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None
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} type;
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void *source;
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@ -136,7 +141,11 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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uint8_t operation_;
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RegisterPair address_, temporary_;
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void decode_base_operation(uint8_t operation) {
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MicroOp **current_instruction_page_;
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MicroOp *base_page_[256];
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MicroOp *ed_page_[256];
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MicroOp *fd_page_[256];
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#define XX {MicroOp::None, 0}
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#define FETCH(x, y) {MicroOp::BusOperation, nullptr, nullptr, {Read, 3, &y.full, &x}}, {MicroOp::Increment16, &y.full}
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@ -164,11 +173,21 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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Program(FETCHL(temporary_.bytes.low, hl_), {MicroOp::op, &temporary_.bytes.low}), \
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Program({MicroOp::op, &a_})
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#define ADD16(d, s) Program(WAIT(4), WAIT(3), {MicroOp::Add16, &s.full, &d.full})
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#define WAIT(n) {MicroOp::BusOperation, nullptr, nullptr, {Internal, n} }
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#define Program(...) { __VA_ARGS__, {MicroOp::MoveToNextProgram} }
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typedef MicroOp InstructionTable[256][20];
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static const MicroOp base_program_table[256][20] = {
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void assemble_page(MicroOp **target, InstructionTable &table) {
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for(int c = 0; c < 256; c++) {
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target[c] = table[c];
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}
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}
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void assemble_base_page(MicroOp **target) {
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InstructionTable base_program_table = {
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{ {MicroOp::MoveToNextProgram} }, /* 0x00 NOP */
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Program(FETCH16(bc_, pc_)), /* 0x01 LD BC, nn */
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XX, /* 0x02 LD (BC), A */
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@ -178,7 +197,7 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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Program(FETCH(bc_.bytes.high, pc_)), /* 0x06 LD B, n */
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XX, /* 0x07 RLCA */
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XX, /* 0x08 EX AF, AF' */
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XX, /* 0x09 ADD HL, BC */
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ADD16(hl_, bc_), /* 0x09 ADD HL, BC */
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Program(FETCHL(a_, bc_)), /* 0x0a LD A, (BC) */
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Program(WAIT(2), {MicroOp::Decrement16, &bc_.full}), /* 0x0b DEC BC */
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XX, /* 0x0c INC C */
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@ -194,7 +213,7 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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Program(FETCH(de_.bytes.high, pc_)), /* 0x16 LD D, n */
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XX, /* 0x17 RLA */
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XX, /* 0x18 JR */
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XX, /* 0x19 ADD HL, DE */
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ADD16(hl_, de_), /* 0x19 ADD HL, DE */
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Program(FETCHL(a_, de_)), /* 0x1a LD A, (DE) */
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Program(WAIT(2), {MicroOp::Decrement16, &de_.full}), /* 0x1b DEC DE */
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XX, /* 0x1c INC E */
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@ -210,7 +229,7 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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Program(FETCH(hl_.bytes.high, pc_)), /* 0x26 LD H, n */
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XX, /* 0x27 DAA */
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XX, /* 0x28 JR Z */
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XX, /* 0x29 ADD HL, HL */
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ADD16(hl_, hl_), /* 0x29 ADD HL, HL */
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Program(FETCH16(address_, pc_), FETCH16L(hl_, address_)), /* 0x2a LD HL, (nn) */
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Program(WAIT(2), {MicroOp::Decrement16, &hl_.full}), /* 0x2b DEC HL */
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XX, /* 0x2c INC L */
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@ -223,10 +242,10 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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Program(WAIT(2), {MicroOp::Increment16, &sp_.full}), /* 0x33 INC SP */
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XX, /* 0x34 INC (HL) */
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XX, /* 0x35 DEC (HL) */
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XX, /* 0x36 LD (HL), n */
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Program(FETCH(temporary_.bytes.low, pc_), STOREL(temporary_.bytes.low, hl_)), /* 0x36 LD (HL), n */
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XX, /* 0x37 SCF */
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XX, /* 0x38 JR C */
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XX, /* 0x39 ADD HL, SP */
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ADD16(hl_, sp_), /* 0x39 ADD HL, SP */
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XX, /* 0x3a LD A, (nn) */
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Program(WAIT(2), {MicroOp::Decrement16, &sp_.full}), /* 0x3b DEC SP */
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XX, /* 0x3c INC A */
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@ -292,9 +311,9 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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XX, /* 0xe8 RET PE */
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XX, /* 0xe9 JP (HL) */
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JP(TestPE), /* 0xea JP PE */
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XX, /* 0xeb EX DE, HL */
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Program({MicroOp::ExDEHL}), /* 0xeb EX DE, HL */
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XX, /* 0xec CALL PE */
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XX, /* 0xed [ED page] */
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Program({MicroOp::SetInstructionPage, ed_page_}), /* 0xed [ED page] */
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XX, /* 0xee XOR n */
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XX, /* 0xef RST 28h */
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XX, /* 0xf0 RET p */
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@ -310,20 +329,23 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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JP(TestM), /* 0xfa JP M */
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XX, /* 0xfb EI */
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XX, /* 0xfc CALL M */
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XX, /* 0xfd [FD page] */
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Program({MicroOp::SetInstructionPage, fd_page_}), /* 0xfd [FD page] */
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XX, /* 0xfe CP n */
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XX, /* 0xff RST 38h */
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};
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if(base_program_table[operation][0].type == MicroOp::None) {
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assemble_page(target, base_program_table);
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}
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void decode_operation(uint8_t operation) {
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if(current_instruction_page_[operation]->type == MicroOp::None) {
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printf("Unknown Z80 operation %02x!!!\n", operation);
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}
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schedule_program(base_program_table[operation]);
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// program_table_ = base_program_table;
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schedule_program(current_instruction_page_[operation]);
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}
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public:
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Processor() {
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// set_base_program_table();
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assemble_base_page(base_page_);
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}
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/*!
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@ -344,6 +366,7 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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#define checkSchedule() \
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if(!scheduled_programs_[schedule_programs_read_pointer_]) {\
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current_instruction_page_ = base_page_;\
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schedule_program(fetch_decode_execute);\
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}
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@ -367,7 +390,7 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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break;
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case MicroOp::DecodeOperation:
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pc_.full++;
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decode_base_operation(operation_);
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decode_operation(operation_);
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break;
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case MicroOp::Increment16: (*(uint16_t *)operation->source)++; break;
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@ -414,6 +437,20 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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#undef set_parity
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case MicroOp::Add16: {
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uint16_t sourceValue = *(uint16_t *)operation->source;
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uint16_t destinationValue = *(uint16_t *)operation->destination;
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int result = sourceValue + destinationValue;
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int halfResult = (sourceValue&0xfff) + (destinationValue&0xfff);
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bit3_result_ = bit5_result_ = (uint8_t)(result >> 8);
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carry_flag_ = (result >> 16) & Flag::Carry;
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half_carry_flag_ = (halfResult >> 8) & Flag::HalfCarry;
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subtract_flag_ = 0;
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*(uint16_t *)operation->destination = (uint16_t)result;
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} break;
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case MicroOp::TestNZ: if(!zero_result_) { move_to_next_program(); checkSchedule(); } break;
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case MicroOp::TestZ: if(zero_result_) { move_to_next_program(); checkSchedule(); } break;
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case MicroOp::TestNC: if(carry_flag_) { move_to_next_program(); checkSchedule(); } break;
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@ -423,6 +460,17 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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case MicroOp::TestP: if(sign_result_ & 0x80) { move_to_next_program(); checkSchedule(); } break;
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case MicroOp::TestM: if(!(sign_result_ & 0x80)) { move_to_next_program(); checkSchedule(); } break;
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case MicroOp::ExDEHL: {
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uint16_t temp = de_.full;
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de_.full = hl_.full;
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hl_.full = temp;
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} break;
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case MicroOp::SetInstructionPage:
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schedule_program(fetch_decode_execute);
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current_instruction_page_ = (CPU::Z80::MicroOp **)operation->source;
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break;
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default:
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// printf("Unhandled Z80 operation %d\n", operation->type);
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return;
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