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mirror of https://github.com/TomHarte/CLK.git synced 2024-12-22 14:30:29 +00:00

Corrects data line loading.

Also adds some extra temporary logging. Outstanding question: why is ATN not being signalled? Is SEL enough?
This commit is contained in:
Thomas Harte 2019-08-17 21:30:59 -04:00
parent 9047932b81
commit 7e001c1d03
2 changed files with 3 additions and 2 deletions

View File

@ -17,6 +17,7 @@ size_t Bus::add_device() {
}
void Bus::set_device_output(size_t device, BusState output) {
printf("%08x output\n", output);
device_states_[device] = output;
state_is_valid_ = false;
}

View File

@ -97,9 +97,9 @@ void NCR5380::write(int address, uint8_t value) {
// Data is output only if the data bus is asserted.
if(assert_data_bus_) {
bus_output_ &= data_bus_;
bus_output_ |= data_bus_;
} else {
bus_output_ |= SCSI::Line::Data;
bus_output_ &= ~SCSI::Line::Data;
}
// In test mode, still nothing is output. Otherwise throw out