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Add CMP, CMPA and TST tests and exclusions.

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This commit is contained in:
Thomas Harte 2022-04-20 16:29:45 -04:00
parent d4fe9d8166
commit 80ff146620
2 changed files with 63 additions and 14 deletions
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64
InstructionSets/68k/Decoder.cpp
View File

@ -142,7 +142,6 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
// case ANDIb: case ANDIl: case ANDIw: // case ANDIb: case ANDIl: case ANDIw:
case SUBIb: case SUBIl: case SUBIw: case SUBIb: case SUBIl: case SUBIw:
case ADDIb: case ADDIl: case ADDIw: case ADDIb: case ADDIl: case ADDIw:
// case CMPIb: case CMPIl: case CMPIw:
switch(original.mode<1>()) { switch(original.mode<1>()) {
default: return original; default: return original;
@ -154,6 +153,23 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
return Preinstruction(); return Preinstruction();
} }
case CMPIb: case CMPIl: case CMPIw:
switch(original.mode<1>()) {
default: return original;
case AddressingMode::ProgramCounterIndirectWithDisplacement:
case AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement:
if constexpr (model >= Model::M68010) {
return original;
}
[[fallthrough]];
case AddressingMode::AddressRegisterDirect:
case AddressingMode::ImmediateData:
case AddressingMode::None:
return Preinstruction();
}
// ADD, SUB, MOVE, MOVEA // ADD, SUB, MOVE, MOVEA
case OpT(Operation::ADDb): case OpT(Operation::ADDw): case OpT(Operation::ADDl): case OpT(Operation::ADDb): case OpT(Operation::ADDw): case OpT(Operation::ADDl):
case OpT(Operation::SUBb): case OpT(Operation::SUBw): case OpT(Operation::SUBl): case OpT(Operation::SUBb): case OpT(Operation::SUBw): case OpT(Operation::SUBl):
@ -251,18 +267,40 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
case AddressingMode::ImmediateData: case AddressingMode::ImmediateData:
return Preinstruction(); return Preinstruction();
} }
//
// case BCHGI: case BSETI: case BCLRI: case OpT(Operation::TSTb): case OpT(Operation::TSTw): case OpT(Operation::TSTl):
// switch(original.mode<1>()) { switch(original.mode<0>()) {
// default: return original; default: return original;
//
// case AddressingMode::None: case AddressingMode::AddressRegisterDirect:
// case AddressingMode::AddressRegisterDirect: if constexpr (op == OpT(Operation::TSTb)) {
// case AddressingMode::ProgramCounterIndirectWithDisplacement: return Preinstruction();
// case AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement: }
// case AddressingMode::ImmediateData: [[fallthrough]];
// return Preinstruction();
// } case AddressingMode::ImmediateData:
if constexpr (model < Model::M68020) {
return Preinstruction();
}
return original;
case AddressingMode::ProgramCounterIndirectWithDisplacement:
case AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement:
if constexpr (model >= Model::M68010) {
return original;
}
[[fallthrough]];
case AddressingMode::None:
return Preinstruction();
}
case OpT(Operation::CMPAw): case OpT(Operation::CMPAl):
switch(original.mode<0>()) {
default: return original;
case AddressingMode::None:
return Preinstruction();
}
} }
} }

11
OSBindings/Mac/Clock SignalTests/m68kDecoderTests.mm
View File

@ -138,6 +138,17 @@ template <int index> NSString *operand(Preinstruction instruction) {
case Operation::BCHG: instruction = @"BCHG"; break; case Operation::BCHG: instruction = @"BCHG"; break;
case Operation::BSET: instruction = @"BSET"; break; case Operation::BSET: instruction = @"BSET"; break;
case Operation::CMPb: instruction = @"CMP.b"; break;
case Operation::CMPw: instruction = @"CMP.w"; break;
case Operation::CMPl: instruction = @"CMP.l"; break;
case Operation::CMPAw: instruction = @"CMPA.w"; break;
case Operation::CMPAl: instruction = @"CMPA.l"; break;
case Operation::TSTb: instruction = @"TST.b"; break;
case Operation::TSTw: instruction = @"TST.w"; break;
case Operation::TSTl: instruction = @"TST.l"; break;
// For now, skip any unmapped operations. // For now, skip any unmapped operations.
default: continue; default: continue;
} }