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Corrects addressing behaviour of nRd[+-].

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This commit is contained in:
Thomas Harte 2019-04-17 08:53:34 -04:00
parent 8f77d1831b
commit 82b08d0e3a
3 changed files with 14 additions and 13 deletions
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10
OSBindings/Mac/Clock SignalTests/QLTests.mm
View File

@ -70,21 +70,21 @@ class QL: public CPU::MC68000::BusHandler {
default: break;
case Microcycle::SelectWord | Microcycle::Read:
// printf("[word r %08x] ", *cycle.address);
cycle.value->full = is_peripheral ? peripheral_result : base[word_address];
if(!(cycle.operation & Microcycle::IsProgram)) printf("[word r %08x -> %04x] ", *cycle.address, cycle.value->full);
break;
case Microcycle::SelectByte | Microcycle::Read:
// printf("[byte r %08x] ", *cycle.address);
cycle.value->halves.low = (is_peripheral ? peripheral_result : base[word_address]) >> cycle.byte_shift();
if(!(cycle.operation & Microcycle::IsProgram)) printf("[byte r %08x -> %02x] ", *cycle.address, cycle.value->halves.low);
break;
case Microcycle::SelectWord:
assert(!(is_rom && !is_peripheral));
// printf("[word w %08x <- %04x] ", *cycle.address, cycle.value->full);
if(!(cycle.operation & Microcycle::IsProgram)) printf("[word w %08x <- %04x] ", *cycle.address, cycle.value->full);
if(!is_peripheral) base[word_address] = cycle.value->full;
break;
case Microcycle::SelectByte:
assert(!(is_rom && !is_peripheral));
// printf("[byte w %08x <- %02x] ", *cycle.address, (cycle.value->full >> cycle.byte_shift()) & 0xff);
if(!(cycle.operation & Microcycle::IsProgram)) printf("[byte w %08x <- %02x] ", *cycle.address, (cycle.value->full >> cycle.byte_shift()) & 0xff);
if(!is_peripheral) base[word_address] = (cycle.value->full & cycle.byte_mask()) | (base[word_address] & (0xffff ^ cycle.byte_mask()));
break;
}
@ -115,7 +115,7 @@ class QL: public CPU::MC68000::BusHandler {
- (void)testStartup {
// This is an example of a functional test case.
// Use XCTAssert and related functions to verify your tests produce the correct results.
_machine->run_for(HalfCycles(40000000));
_machine->run_for(HalfCycles(16000000));
}
@end

14
Processors/68000/Implementation/68000Implementation.hpp
View File

@ -52,13 +52,13 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
// no instruction was ongoing. Either way, do a standard instruction operation.
// TODO: unless an interrupt is pending, or the trap flag is set.
if(address_[5].full > 0x3fff0 || program_counter_.full < 0x16a) {
std::cout << std::setfill('0');
std::cout << (extend_flag_ ? 'x' : '-') << (negative_flag_ ? 'n' : '-') << (zero_result_ ? '-' : 'z');
std::cout << (overflow_flag_ ? 'v' : '-') << (carry_flag_ ? 'c' : '-') << '\t';
for(int c = 0; c < 8; ++ c) std::cout << "d" << c << ":" << std::setw(8) << data_[c].full << " ";
for(int c = 0; c < 8; ++ c) std::cout << "a" << c << ":" << std::setw(8) << address_[c].full << " ";
}
// if(program_counter_.full >= 0x25c && program_counter_.full < 0x286) {
// std::cout << std::setfill('0');
// std::cout << (extend_flag_ ? 'x' : '-') << (negative_flag_ ? 'n' : '-') << (zero_result_ ? '-' : 'z');
// std::cout << (overflow_flag_ ? 'v' : '-') << (carry_flag_ ? 'c' : '-') << '\t';
// for(int c = 0; c < 8; ++ c) std::cout << "d" << c << ":" << std::setw(8) << data_[c].full << " ";
// for(int c = 0; c < 8; ++ c) std::cout << "a" << c << ":" << std::setw(8) << address_[c].full << " ";
// }
std::cout << '\n';
decoded_instruction_ = prefetch_queue_.halves.high.full;

3
Processors/68000/Implementation/68000Storage.cpp
View File

@ -239,7 +239,8 @@ struct ProcessorStorageConstructor {
step.microcycle.length = HalfCycles(3);
step.microcycle.operation |= (read_full_words ? Microcycle::SelectWord : Microcycle::SelectByte) | (is_read ? Microcycle::Read : 0);
if(post_adjustment) {
if(tolower(token[1]) == 'r') {
// nr and nR should affect address 0; nw, nW, nrd and nRd should affect address 1.
if(tolower(token[1]) == 'r' && token.size() == 2) {
step.action = (post_adjustment > 0) ? Action::IncrementEffectiveAddress0 : Action::DecrementEffectiveAddress0;
} else {
step.action = (post_adjustment > 0) ? Action::IncrementEffectiveAddress1 : Action::DecrementEffectiveAddress1;