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Adjust CGA clocking down by 1/7th.
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@ -30,11 +30,12 @@ class CGA {
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void run_for(Cycles cycles) {
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void run_for(Cycles cycles) {
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// Input rate is the PIT rate of 1,193,182 Hz.
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// Input rate is the PIT rate of 1,193,182 Hz.
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// CGA is clocked at the real oscillator rate of 14 times that.
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// CGA is clocked at the real oscillator rate of 12 times that.
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// But there's also an internal divide by 8 to align to the fetch clock.
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// But there's also an internal divide by 8 to align to the 80-cfetch clock.
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full_clock_ += 7 * cycles.as<int>();
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// ... and 12/8 = 3/2.
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full_clock_ += 3 * cycles.as<int>();
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const int modulo = 4 * outputter_.clock_divider;
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const int modulo = 2 * outputter_.clock_divider;
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crtc_.run_for(Cycles(full_clock_ / modulo));
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crtc_.run_for(Cycles(full_clock_ / modulo));
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full_clock_ %= modulo;
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full_clock_ %= modulo;
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}
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}
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@ -90,7 +91,7 @@ class CGA {
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}
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}
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Outputs::Display::ScanStatus get_scaled_scan_status() const {
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Outputs::Display::ScanStatus get_scaled_scan_status() const {
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return outputter_.crt.get_scaled_scan_status() * 4.0f / (7.0f * 8.0f);
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return outputter_.crt.get_scaled_scan_status() * float(outputter_.clock_divider) / (3.0f * 4.0f);
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}
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}
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private:
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private:
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