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https://github.com/TomHarte/CLK.git
synced 2024-11-21 21:33:54 +00:00
Makes a first attempt at some sort of interrupt functionality.
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e671cc6056
commit
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@ -82,6 +82,7 @@ class ConcreteMachine:
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const auto changes = chipset_.run_for(cycle.length);
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cia_a_.advance_tod(changes.vsyncs);
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cia_b_.advance_tod(changes.hsyncs);
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mc68000_.set_interrupt_level(changes.interrupt_level);
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// Check for assertion of reset.
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if(cycle.operation & Microcycle::Reset) {
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@ -89,6 +90,13 @@ class ConcreteMachine:
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LOG("Reset; PC is around " << PADHEX(8) << mc68000_.get_state().program_counter);
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}
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// Autovector interrupts.
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if(cycle.operation & Microcycle::InterruptAcknowledge) {
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mc68000_.set_is_peripheral_address(true);
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} else {
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mc68000_.set_is_peripheral_address(false);
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}
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// Do nothing if no address is exposed.
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if(!(cycle.operation & (Microcycle::NewAddress | Microcycle::SameAddress))) return HalfCycles(0);
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@ -16,6 +16,27 @@
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using namespace Amiga;
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namespace {
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enum InterruptFlag: uint16_t {
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SerialPortTransmit = 1 << 0,
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DiskBlock = 1 << 1,
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Software = 1 << 2,
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IOPortsAndTimers = 1 << 3,
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Copper = 1 << 4,
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VerticalBlank = 1 << 5,
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Blitter = 1 << 6,
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AudioChannel0 = 1 << 7,
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AudioChannel1 = 1 << 8,
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AudioChannel2 = 1 << 9,
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AudioChannel3 = 1 << 10,
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SerialPortReceive = 1 << 11,
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DiskSyncMatch = 1 << 12,
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External = 1 << 13,
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};
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}
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Chipset::Chipset(uint16_t *ram, size_t size) :
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blitter_(ram, size) {
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}
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@ -33,9 +54,37 @@ Chipset::Changes Chipset::run_for(HalfCycles length) {
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changes.vsyncs = y_ / 312;
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y_ %= 312;
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// y = 0 => start of vertical blank.
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if(changes.vsyncs) {
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interrupt_requests_ |= InterruptFlag::VerticalBlank;
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update_interrupts();
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}
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changes.interrupt_level = interrupt_level_;
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return changes;
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}
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void Chipset::update_interrupts() {
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interrupt_level_ = 0;
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const uint16_t enabled_requests = interrupt_enable_ & interrupt_requests_ & 0x3fff;
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if(enabled_requests && (interrupt_enable_ & 0x4000)) {
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if(enabled_requests & (InterruptFlag::External)) {
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interrupt_level_ = 6;
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} else if(enabled_requests & (InterruptFlag::SerialPortReceive | InterruptFlag::DiskSyncMatch)) {
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interrupt_level_ = 5;
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} else if(enabled_requests & (InterruptFlag::AudioChannel0 | InterruptFlag::AudioChannel1 | InterruptFlag::AudioChannel2 | InterruptFlag::AudioChannel3)) {
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interrupt_level_ = 4;
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} else if(enabled_requests & (InterruptFlag::Copper | InterruptFlag::VerticalBlank | InterruptFlag::Blitter)) {
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interrupt_level_ = 3;
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} else if(enabled_requests & (InterruptFlag::External)) {
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interrupt_level_ = 2;
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} else if(enabled_requests & (InterruptFlag::SerialPortTransmit | InterruptFlag::DiskBlock | InterruptFlag::Software)) {
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interrupt_level_ = 1;
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}
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}
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}
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void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
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using Microcycle = CPU::MC68000::Microcycle;
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@ -119,11 +168,18 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
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update_interrupts();
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LOG("Interrupt enable mask modified by " << PADHEX(4) << cycle.value16() << "; is now " << std::bitset<16>{interrupt_enable_});
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break;
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case Read(0x01c):
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cycle.set_value16(interrupt_enable_);
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break;
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case Write(0x09c):
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ApplySetClear(interrupt_requests_);
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update_interrupts();
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LOG("Interrupt request modified by " << PADHEX(4) << cycle.value16() << "; is now " << std::bitset<16>{interrupt_requests_});
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break;
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case Read(0x01e):
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cycle.set_value16(interrupt_requests_);
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break;
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// Display management.
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case Write(0x08e): {
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@ -29,7 +29,7 @@ class Chipset {
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struct Changes {
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int hsyncs = 0;
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int vsyncs = 0;
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// TODO: interrupt change?
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int interrupt_level = 0;
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};
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/// Advances the stated amount of time.
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@ -38,15 +38,19 @@ class Chipset {
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/// Performs the provided microcycle, which the caller guarantees to be a memory access.
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void perform(const CPU::MC68000::Microcycle &);
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/// Provides the chipset's current interrupt level.
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int get_interrupt_level() {
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return interrupt_level_;
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}
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private:
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// MARK: - Interrupts.
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uint16_t interrupt_enable_ = 0;
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uint16_t interrupt_requests_ = 0;
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int interrupt_level_ = 0;
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void update_interrupts() {
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// TODO.
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}
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void update_interrupts();
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// MARK: - DMA Control and Blitter.
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