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Fix base address, delays.
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5ca1659bcc
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@ -310,7 +310,7 @@ uint8_t VideoOutput::run_for(const Cycles cycles) {
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output_ = stage;
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if(stage == OutputStage::Pixels) {
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initial_output_target_ = current_output_target_ = crt_.begin_data(mode_40 ? 320 : 640);
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initial_output_target_ = current_output_target_ = crt_.begin_data(640);//crt_.begin_data(mode_40 ? 320 : 640);
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}
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}
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++output_length_;
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@ -352,15 +352,15 @@ uint8_t VideoOutput::run_for(const Cycles cycles) {
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void VideoOutput::write(int address, uint8_t value) {
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switch(address & 0xf) {
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case 0x02:
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screen_base =
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(screen_base & 0b0111'1110'0000'0000) |
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((value << 1) & 0b0000'0001'1100'0000);
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break;
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case 0x03:
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screen_base =
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(screen_base & 0b0111'1110'0000'0000) |
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((value << 1) & 0b0000'0001'1100'0000);
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break;
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case 0x03:
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screen_base =
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((value << 9) & 0b0111'1110'0000'0000) |
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(screen_base & 0b0000'0001'1100'0000);
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break;
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case 0x07: {
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uint8_t mode = (value >> 3)&7;
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mode_40 = mode >= 4;
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@ -59,7 +59,7 @@ class VideoOutput {
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/// RAM access that is first signalled in the upcoming cycle.
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Cycles ram_delay() {
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if(!mode_40 && !in_blank()) {
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return 2 + h_active - h_count;
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return 2 + ((h_active - h_count) >> 3);
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}
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return io_delay();
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}
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