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Remove errant spaces.

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This commit is contained in:
Thomas Harte 2024-12-01 09:04:32 -05:00
parent 43fcf46d69
commit 8b88d1294d
18 changed files with 51 additions and 51 deletions
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2
Components/8272/Results.hpp
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@ -52,7 +52,7 @@ public:
}
/// @returns @c true if all result bytes are exhausted; @c false otherwise.
bool empty() const { return result_.empty(); }
bool empty() const { return result_.empty(); }
/// @returns The next byte of the result.
uint8_t next() {

10
Components/8272/Status.hpp
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@ -38,7 +38,7 @@ enum class Status0: uint8_t {
enum class Status1: uint8_t {
EndOfCylinder = 0x80,
DataError = 0x20,
DataError = 0x20,
OverRun = 0x10,
NoData = 0x04,
NotWriteable = 0x02,
@ -47,7 +47,7 @@ enum class Status1: uint8_t {
enum class Status2: uint8_t {
DeletedControlMark = 0x40,
DataCRCError = 0x20,
DataCRCError = 0x20,
WrongCyinder = 0x10,
ScanEqualHit = 0x08,
ScanNotSatisfied = 0x04,
@ -57,7 +57,7 @@ enum class Status2: uint8_t {
enum class Status3: uint8_t {
Fault = 0x80,
WriteProtected = 0x40,
WriteProtected = 0x40,
Ready = 0x20,
Track0 = 0x10,
TwoSided = 0x08,
@ -91,9 +91,9 @@ public:
void set(const MainStatus flag, const bool value) {
set(uint8_t(flag), value, main_status_);
}
void start_seek(const int drive) { main_status_ |= 1 << drive; }
void start_seek(const int drive) { main_status_ |= 1 << drive; }
void set(const Status0 flag) { set(uint8_t(flag), true, status_[0]); }
void set(const Status1 flag) { set(uint8_t(flag), true, status_[1]); }
void set(const Status1 flag) { set(uint8_t(flag), true, status_[1]); }
void set(const Status2 flag) { set(uint8_t(flag), true, status_[2]); }
void set_status0(uint8_t value) { status_[0] = value; }

4
InstructionSets/ARM/OperationMapper.hpp
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@ -323,7 +323,7 @@ struct CoprocessorDataOperation {
constexpr CoprocessorDataOperation(const uint32_t opcode) noexcept : opcode_(opcode) {}
uint32_t operand1() const { return (opcode_ >> 16) & 0xf; }
uint32_t operand2() const { return opcode_ & 0xf; }
uint32_t operand2() const { return opcode_ & 0xf; }
uint32_t destination() const { return (opcode_ >> 12) & 0xf; }
uint32_t coprocessor() const { return (opcode_ >> 8) & 0xf; }
uint32_t information() const { return (opcode_ >> 5) & 0x7; }
@ -356,7 +356,7 @@ struct CoprocessorRegisterTransfer {
constexpr CoprocessorRegisterTransfer(const uint32_t opcode) noexcept : opcode_(opcode) {}
uint32_t operand1() const { return (opcode_ >> 16) & 0xf; }
uint32_t operand2() const { return opcode_ & 0xf; }
uint32_t operand2() const { return opcode_ & 0xf; }
uint32_t destination() const { return (opcode_ >> 12) & 0xf; }
uint32_t coprocessor() const { return (opcode_ >> 8) & 0xf; }
uint32_t information() const { return (opcode_ >> 5) & 0x7; }

2
InstructionSets/ARM/Registers.hpp
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@ -194,7 +194,7 @@ struct Registers {
const auto r14 = pc_status(pc_offset_during(type));
switch(type) {
case Exception::IRQ: set_mode(Mode::IRQ); break;
case Exception::FIQ: set_mode(Mode::FIQ); break;
case Exception::FIQ: set_mode(Mode::FIQ); break;
default: set_mode(Mode::Supervisor); break;
}
active_[14] = r14;

4
InstructionSets/x86/Implementation/PerformImplementation.hpp
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@ -119,12 +119,12 @@ template <
// The two following return the high and low parts of that pair; they also work in Byte mode to return AH:AL,
// i.e. AX split into high and low parts.
const auto pair_high = [&]() -> IntT& {
if constexpr (data_size == DataSize::Byte) return context.registers.ah();
if constexpr (data_size == DataSize::Byte) return context.registers.ah();
else if constexpr (data_size == DataSize::Word) return context.registers.dx();
else if constexpr (data_size == DataSize::DWord) return context.registers.edx();
};
const auto pair_low = [&]() -> IntT& {
if constexpr (data_size == DataSize::Byte) return context.registers.al();
if constexpr (data_size == DataSize::Byte) return context.registers.al();
else if constexpr (data_size == DataSize::Word) return context.registers.ax();
else if constexpr (data_size == DataSize::DWord) return context.registers.eax();
};

24
InstructionSets/x86/Implementation/Resolver.hpp
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@ -68,42 +68,42 @@ IntT *register_(ContextT &context) {
//
// (i) does the `constexpr` version of a `switch`; and
// (i) ensures .eax() etc aren't called on @c registers for 16-bit processors, so they need not implement 32-bit storage.
if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.eax(); }
if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.eax(); }
else if constexpr (std::is_same_v<IntT, uint16_t>) { return &context.registers.ax(); }
else if constexpr (std::is_same_v<IntT, uint8_t>) { return &context.registers.al(); }
else { return nullptr; }
else { return nullptr; }
case Source::eCX:
if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.ecx(); }
if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.ecx(); }
else if constexpr (std::is_same_v<IntT, uint16_t>) { return &context.registers.cx(); }
else if constexpr (std::is_same_v<IntT, uint8_t>) { return &context.registers.cl(); }
else { return nullptr; }
else { return nullptr; }
case Source::eDX:
if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.edx(); }
if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.edx(); }
else if constexpr (std::is_same_v<IntT, uint16_t>) { return &context.registers.dx(); }
else if constexpr (std::is_same_v<IntT, uint8_t>) { return &context.registers.dl(); }
else if constexpr (std::is_same_v<IntT, uint32_t>) { return nullptr; }
case Source::eBX:
if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.ebx(); }
if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.ebx(); }
else if constexpr (std::is_same_v<IntT, uint16_t>) { return &context.registers.bx(); }
else if constexpr (std::is_same_v<IntT, uint8_t>) { return &context.registers.bl(); }
else if constexpr (std::is_same_v<IntT, uint32_t>) { return nullptr; }
case Source::eSPorAH:
if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.esp(); }
if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.esp(); }
else if constexpr (std::is_same_v<IntT, uint16_t>) { return &context.registers.sp(); }
else if constexpr (std::is_same_v<IntT, uint8_t>) { return &context.registers.ah(); }
else { return nullptr; }
case Source::eBPorCH:
if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.ebp(); }
if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.ebp(); }
else if constexpr (std::is_same_v<IntT, uint16_t>) { return &context.registers.bp(); }
else if constexpr (std::is_same_v<IntT, uint8_t>) { return &context.registers.ch(); }
else { return nullptr; }
else { return nullptr; }
case Source::eSIorDH:
if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.esi(); }
if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.esi(); }
else if constexpr (std::is_same_v<IntT, uint16_t>) { return &context.registers.si(); }
else if constexpr (std::is_same_v<IntT, uint8_t>) { return &context.registers.dh(); }
else { return nullptr; }
else { return nullptr; }
case Source::eDIorBH:
if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.edi(); }
if constexpr (supports_dword && std::is_same_v<IntT, uint32_t>) { return &context.registers.edi(); }
else if constexpr (std::is_same_v<IntT, uint16_t>) { return &context.registers.di(); }
else if constexpr (std::is_same_v<IntT, uint8_t>) { return &context.registers.bh(); }
else { return nullptr; }

2
InstructionSets/x86/Instruction.cpp
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@ -487,7 +487,7 @@ std::string InstructionSet::x86::to_string(
case Operation::OUTS:
case Operation::OUTS_REP:
switch(instruction.second.data_segment()) {
default: break;
default: break;
case Source::ES: operation += "es "; break;
case Source::CS: operation += "cs "; break;
case Source::DS: operation += "ds "; break;

2
Machines/Acorn/Archimedes/Archimedes.cpp
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@ -69,7 +69,7 @@ class ConcreteMachine:
// This is a 24-cycle window, so at 24Mhz macro_tick() is called at 1Mhz.
// Hence, required ticks are:
//
// * CPU: 24;
// * CPU: 24;
// * video: 24 / video_divider;
// * floppy: 8;
// * timers: 2;

14
Machines/Acorn/Archimedes/InputOutputController.hpp
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@ -165,7 +165,7 @@ struct InputOutputController: public ClockingHint::Observer {
//
// fast/1 = FDC
// sync/2 = econet
// sync/3 = serial line
// sync/3 = serial line
//
// bank 4 = podules
//
@ -410,7 +410,7 @@ struct InputOutputController: public ClockingHint::Observer {
// b0: ?
// b1: double/single density; 0 = double.
// b2: ?
// b3: floppy drive reset; 0 = reset.
// b3: floppy drive reset; 0 = reset.
// b4: printer strobe
// b5: ?
// b6: ?
@ -474,12 +474,12 @@ struct InputOutputController: public ClockingHint::Observer {
return true;
}
auto &sound() { return sound_; }
auto &sound() { return sound_; }
const auto &sound() const { return sound_; }
auto &video() { return video_; }
const auto &video() const { return video_; }
auto &keyboard() { return keyboard_; }
const auto &keyboard() const { return keyboard_; }
auto &video() { return video_; }
const auto &video() const { return video_; }
auto &keyboard() { return keyboard_; }
const auto &keyboard() const { return keyboard_; }
void update_interrupts() {
const auto set = [&](Interrupt &target, uint8_t flag, bool set) {

4
Machines/Acorn/Archimedes/MemoryController.hpp
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@ -225,8 +225,8 @@ struct MemoryController {
return ioc_.sound().speaker();
}
auto &sound() { return ioc_.sound(); }
const auto &sound() const { return ioc_.sound(); }
auto &sound() { return ioc_.sound(); }
const auto &sound() const { return ioc_.sound(); }
auto &video() { return ioc_.video(); }
const auto &video() const { return ioc_.video(); }
auto &keyboard() { return ioc_.keyboard(); }

4
Machines/Acorn/Archimedes/Video.hpp
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@ -225,7 +225,7 @@ struct Video {
return vertical_state_.phase() != Phase::Display;
}
void set_frame_start(uint32_t address) {
void set_frame_start(uint32_t address) {
frame_start_ = address;
++frame_start_sets_;
}
@ -233,7 +233,7 @@ struct Video {
void set_buffer_end(uint32_t address) { buffer_end_ = address; }
void set_cursor_start(uint32_t address) { cursor_start_ = address; }
Outputs::CRT::CRT &crt() { return crt_; }
Outputs::CRT::CRT &crt() { return crt_; }
const Outputs::CRT::CRT &crt() const { return crt_; }
int clock_divider() const {

4
Machines/MSX/MSX.cpp
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@ -1039,13 +1039,13 @@ std::unique_ptr<Machine> Machine::MSX(const Analyser::Static::Target *target, co
const auto msx_target = dynamic_cast<const Target *>(target);
if(msx_target->has_msx_music) {
switch(msx_target->model) {
default: return nullptr;
default: return nullptr;
case Target::Model::MSX1: return std::make_unique<ConcreteMachine<Target::Model::MSX1, true>>(*msx_target, rom_fetcher);
case Target::Model::MSX2: return std::make_unique<ConcreteMachine<Target::Model::MSX2, true>>(*msx_target, rom_fetcher);
}
} else {
switch(msx_target->model) {
default: return nullptr;
default: return nullptr;
case Target::Model::MSX1: return std::make_unique<ConcreteMachine<Target::Model::MSX1, false>>(*msx_target, rom_fetcher);
case Target::Model::MSX2: return std::make_unique<ConcreteMachine<Target::Model::MSX2, false>>(*msx_target, rom_fetcher);
}

2
Machines/PCCompatible/MDA.hpp
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@ -116,7 +116,7 @@ class MDA {
if(count) {
switch(output_state) {
case OutputState::Sync: crt.output_sync(count); break;
case OutputState::Border: crt.output_blank(count); break;
case OutputState::Border: crt.output_blank(count); break;
case OutputState::Pixels:
crt.output_data(count);
pixels = pixel_pointer = nullptr;

4
Machines/PCCompatible/PCCompatible.cpp
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@ -362,7 +362,7 @@ class KeyboardController {
const auto last_mode = mode_;
mode_ = Mode(mode);
switch(mode_) {
case Mode::NormalOperation: break;
case Mode::NormalOperation: break;
case Mode::NoIRQsIgnoreInput:
pic_.apply_edge<1>(false);
break;
@ -932,7 +932,7 @@ class ConcreteMachine:
void run_for(const Cycles duration) override {
switch(speed_) {
case Target::Speed::ApproximatelyOriginal: run_for<Target::Speed::ApproximatelyOriginal>(duration); break;
case Target::Speed::Fast: run_for<Target::Speed::Fast>(duration); break;
case Target::Speed::Fast: run_for<Target::Speed::Fast>(duration); break;
}
}

2
Machines/Sinclair/ZX8081/ZX8081.cpp
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@ -39,7 +39,7 @@ namespace {
// TODO:
// Quiksilva sound support:
// 7FFFh.W PSG index
// 7FFFh.W PSG index
// 7FFEh.R/W PSG data
namespace Sinclair {

8
Numeric/Carry.hpp
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@ -13,8 +13,8 @@
namespace Numeric {
/// @returns @c true if from @c bit there was:
/// • carry after calculating @c lhs + @c rhs if @c is_add is true; or
/// • borrow after calculating @c lhs - @c rhs if @c is_add is false;
/// • carry after calculating @c lhs + @c rhs if @c is_add is true; or
/// • borrow after calculating @c lhs - @c rhs if @c is_add is false;
/// producing @c result.
template <bool is_add, int bit, typename IntT> bool carried_out(IntT lhs, IntT rhs, IntT result) {
// Additive:
@ -40,8 +40,8 @@ template <bool is_add, int bit, typename IntT> bool carried_out(IntT lhs, IntT r
}
/// @returns @c true if there was carry into @c bit when computing either:
/// • @c lhs + @c rhs; or
/// • @c lhs - @c rhs;
/// • @c lhs + @c rhs; or
/// • @c lhs - @c rhs;
/// producing @c result.
template <int bit, typename IntT> bool carried_in(IntT lhs, IntT rhs, IntT result) {
// 0 and 0 or 1 and 1 => did if 1.

2
Processors/6502/Implementation/6502Storage.hpp
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@ -188,7 +188,7 @@ class ProcessorStorage {
CycleAddSignedOperandToPC, // sets next_address to PC + (signed)operand. If the high byte of next_address differs from the PC, schedules a throwaway read from the half-updated PC. 65C02 specific: if the top two bytes are the same, proceeds directly to fetch-decode-execute, ignoring any pending interrupts.
OperationAddSignedOperandToPC16, // adds (signed)operand into the PC, leaving old PC in next_address_ and skipping a program step if there was no carry from low to high byte
CycleFetchFromNextAddress, // performs a throwaway fetch from next_address_
CycleFetchFromNextAddress, // performs a throwaway fetch from next_address_
OperationSetFlagsFromOperand, // sets all flags based on operand_
OperationSetOperandFromFlagsWithBRKSet, // sets operand_ to the value of all flags, with the break flag set

8
Reflection/Dispatcher.hpp
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@ -56,10 +56,10 @@ static constexpr int switch_max = 2048;
/// Provides glue for a run of calls like:
///
/// SequencerT.perform<0>(...)
/// SequencerT.perform<1>(...)
/// SequencerT.perform<2>(...)
/// ...etc...
/// SequencerT.perform<0>(...)
/// SequencerT.perform<1>(...)
/// SequencerT.perform<2>(...)
/// ...etc...
///
/// Allowing the caller to execute any subrange of the calls.
template <typename SequencerT>