mirror of
https://github.com/TomHarte/CLK.git
synced 2024-12-27 16:31:31 +00:00
Fixed ROM loading by the Electron, turned the WD1770 into a 'disk drive' (it'll do for now), persuaded it to get all the way through a very specifically convenient type 1 command.
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parent
7a34ae0da6
commit
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@ -8,13 +8,17 @@
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#include "1770.hpp"
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using namespace WD;
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WD1770::WD1770() : state_(State::Waiting), status_(0), has_command_(false) {}
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WD1770::WD1770() :
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Storage::Disk::Drive(1000000, 8, 300),
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state_(State::Waiting), status_(0), has_command_(false) {}
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void WD1770::set_drive(std::shared_ptr<Storage::Disk::Drive> drive)
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{
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}
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//void WD1770::set_disk(std::shared_ptr<Storage::Disk::Disk> disk)
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//{
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// drive_.reset(new Storage::Disk::Drive(1000000, 8, 300));
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//}
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void WD1770::set_is_double_density(bool is_double_density)
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{
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@ -123,8 +127,27 @@ void WD1770::run_for_cycles(unsigned int number_of_cycles)
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state_ = State::TestHead;
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continue;
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// case State::TestHead:
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// break;
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case State::TestHead:
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if(get_is_track_zero() && !is_step_in_)
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{
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track_ = 0;
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state_ = State::TestVerify;
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}
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else
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{
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step(is_step_in_ ? 1 : -1);
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state_ = State::StepDelay;
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step_delay_.count = 0;
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}
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break;
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case State::StepDelay:
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if(step_delay_.count == (command_&3))
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{
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state_ = (command_ >> 5) ? State::TestVerify : State::TestTrack;
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}
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step_delay_.count++;
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break;
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case State::TestVerify:
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if(command_ & 0x04)
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@ -167,3 +190,11 @@ void WD1770::run_for_cycles(unsigned int number_of_cycles)
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}
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}
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}
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void WD1770::process_input_bit(int value, unsigned int cycles_since_index_hole)
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{
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}
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void WD1770::process_index_hole()
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{
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}
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@ -13,11 +13,11 @@
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namespace WD {
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class WD1770 {
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class WD1770: public Storage::Disk::Drive {
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public:
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WD1770();
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void set_drive(std::shared_ptr<Storage::Disk::Drive> drive);
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// void set_disk(std::shared_ptr<Storage::Disk::Disk> disk);
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void set_is_double_density(bool is_double_density);
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void set_register(int address, uint8_t value);
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uint8_t get_register(int address);
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@ -47,7 +47,8 @@ class WD1770 {
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BeginType1PostSpin,
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WaitForSixIndexPulses,
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TestTrack, TestDirection, TestHead,
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TestVerify, VerifyTrack
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TestVerify, VerifyTrack,
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StepDelay
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} state_;
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union {
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@ -55,6 +56,9 @@ class WD1770 {
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int count;
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State next_state;
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} wait_six_index_pulses_;
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struct {
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int count;
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} step_delay_;
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};
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uint8_t status_;
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@ -67,6 +71,9 @@ class WD1770 {
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void set_interrupt_request(bool interrupt_request) {}
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bool is_step_in_;
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uint8_t data_shift_register_;
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virtual void process_input_bit(int value, unsigned int cycles_since_index_hole);
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virtual void process_index_hole();
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};
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}
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@ -499,7 +499,14 @@ void Machine::configure_as_target(const StaticAnalyser::Target &target)
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set_rom(ROMSlot0, _dfs);
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}
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// TODO: actually insert the disk, why not?
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_wd1770->set_disk(target.disks.front());
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}
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ROMSlot slot = ROMSlot12;
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for(std::shared_ptr<Storage::Cartridge::Cartridge> cartridge : target.cartridges)
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{
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set_rom(slot, cartridge->get_segments().front().data);
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slot = (ROMSlot)(((int)slot + 1)&15);
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}
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if(target.loadingCommand.length()) // TODO: and automatic loading option enabled
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