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mirror of https://github.com/TomHarte/CLK.git synced 2024-12-27 16:31:31 +00:00

Fixed ROM loading by the Electron, turned the WD1770 into a 'disk drive' (it'll do for now), persuaded it to get all the way through a very specifically convenient type 1 command.

This commit is contained in:
Thomas Harte 2016-09-20 22:14:33 -04:00
parent 7a34ae0da6
commit 8db0030068
3 changed files with 55 additions and 10 deletions

View File

@ -8,13 +8,17 @@
#include "1770.hpp"
using namespace WD;
WD1770::WD1770() : state_(State::Waiting), status_(0), has_command_(false) {}
WD1770::WD1770() :
Storage::Disk::Drive(1000000, 8, 300),
state_(State::Waiting), status_(0), has_command_(false) {}
void WD1770::set_drive(std::shared_ptr<Storage::Disk::Drive> drive)
{
}
//void WD1770::set_disk(std::shared_ptr<Storage::Disk::Disk> disk)
//{
// drive_.reset(new Storage::Disk::Drive(1000000, 8, 300));
//}
void WD1770::set_is_double_density(bool is_double_density)
{
@ -123,8 +127,27 @@ void WD1770::run_for_cycles(unsigned int number_of_cycles)
state_ = State::TestHead;
continue;
// case State::TestHead:
// break;
case State::TestHead:
if(get_is_track_zero() && !is_step_in_)
{
track_ = 0;
state_ = State::TestVerify;
}
else
{
step(is_step_in_ ? 1 : -1);
state_ = State::StepDelay;
step_delay_.count = 0;
}
break;
case State::StepDelay:
if(step_delay_.count == (command_&3))
{
state_ = (command_ >> 5) ? State::TestVerify : State::TestTrack;
}
step_delay_.count++;
break;
case State::TestVerify:
if(command_ & 0x04)
@ -167,3 +190,11 @@ void WD1770::run_for_cycles(unsigned int number_of_cycles)
}
}
}
void WD1770::process_input_bit(int value, unsigned int cycles_since_index_hole)
{
}
void WD1770::process_index_hole()
{
}

View File

@ -13,11 +13,11 @@
namespace WD {
class WD1770 {
class WD1770: public Storage::Disk::Drive {
public:
WD1770();
void set_drive(std::shared_ptr<Storage::Disk::Drive> drive);
// void set_disk(std::shared_ptr<Storage::Disk::Disk> disk);
void set_is_double_density(bool is_double_density);
void set_register(int address, uint8_t value);
uint8_t get_register(int address);
@ -47,7 +47,8 @@ class WD1770 {
BeginType1PostSpin,
WaitForSixIndexPulses,
TestTrack, TestDirection, TestHead,
TestVerify, VerifyTrack
TestVerify, VerifyTrack,
StepDelay
} state_;
union {
@ -55,6 +56,9 @@ class WD1770 {
int count;
State next_state;
} wait_six_index_pulses_;
struct {
int count;
} step_delay_;
};
uint8_t status_;
@ -67,6 +71,9 @@ class WD1770 {
void set_interrupt_request(bool interrupt_request) {}
bool is_step_in_;
uint8_t data_shift_register_;
virtual void process_input_bit(int value, unsigned int cycles_since_index_hole);
virtual void process_index_hole();
};
}

View File

@ -499,7 +499,14 @@ void Machine::configure_as_target(const StaticAnalyser::Target &target)
set_rom(ROMSlot0, _dfs);
}
// TODO: actually insert the disk, why not?
_wd1770->set_disk(target.disks.front());
}
ROMSlot slot = ROMSlot12;
for(std::shared_ptr<Storage::Cartridge::Cartridge> cartridge : target.cartridges)
{
set_rom(slot, cartridge->get_segments().front().data);
slot = (ROMSlot)(((int)slot + 1)&15);
}
if(target.loadingCommand.length()) // TODO: and automatic loading option enabled