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mirror of https://github.com/TomHarte/CLK.git synced 2025-01-11 08:30:55 +00:00

Ensures timer-linked PB7 output is actually output.

This commit is contained in:
Thomas Harte 2020-09-20 15:03:26 -04:00
parent 703065a0a5
commit 8e242eea54
2 changed files with 14 additions and 2 deletions

View File

@ -135,6 +135,7 @@ template <class T> class MOS6522: public MOS6522Storage {
/// if this affects the visible output, it will be passed to the handler.
void set_control_line_output(Port port, Line line, LineState value);
void evaluate_cb2_output();
void evaluate_port_b_output();
};
}

View File

@ -43,7 +43,7 @@ template <typename T> void MOS6522<T>::write(int address, uint8_t value) {
registers_.output[1] = value;
bus_handler_.run_for(time_since_bus_handler_call_.flush<HalfCycles>());
bus_handler_.set_port_output(Port::B, value, registers_.data_direction[1]);
evaluate_port_b_output();
registers_.interrupt_flags &= ~(InterruptFlag::CB1ActiveEdge | ((registers_.peripheral_control&0x20) ? 0 : InterruptFlag::CB2ActiveEdge));
reevaluate_interrupts();
@ -88,6 +88,7 @@ template <typename T> void MOS6522<T>::write(int address, uint8_t value) {
// If PB7 output mode is active, set it low.
if(registers_.auxiliary_control & 0x80) {
registers_.timer_port_b_output &= 0x7f;
evaluate_port_b_output();
}
// Clear existing interrupt flag.
@ -124,6 +125,7 @@ template <typename T> void MOS6522<T>::write(int address, uint8_t value) {
if(!(registers_.auxiliary_control & 0x80)) {
registers_.timer_port_b_output |= 0x80;
}
evaluate_port_b_output();
break;
case 0xc: { // Peripheral control ('PCR').
// const auto old_peripheral_control = registers_.peripheral_control;
@ -368,11 +370,20 @@ template <typename T> void MOS6522<T>::do_phase1() {
if(registers_.auxiliary_control&0x80) {
registers_.timer_port_b_output ^= 0x80;
bus_handler_.run_for(time_since_bus_handler_call_.flush<HalfCycles>());
bus_handler_.set_port_output(Port::B, registers_.output[1], registers_.data_direction[1]);
evaluate_port_b_output();
}
}
}
template <typename T> void MOS6522<T>::evaluate_port_b_output() {
// Apply current timer-linked PB7 output if any atop the stated output.
const uint8_t timer_control_bit = registers_.auxiliary_control & 0x80;
bus_handler_.set_port_output(
Port::B,
(registers_.output[1] & (0xff ^ timer_control_bit)) | timer_control_bit,
registers_.data_direction[1] | timer_control_bit);
}
/*! Runs for a specified number of half cycles. */
template <typename T> void MOS6522<T>::run_for(const HalfCycles half_cycles) {
auto number_of_half_cycles = half_cycles.as_integral();