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Correct ADDA/SUBA timing.

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This commit is contained in:
Thomas Harte 2022-06-01 15:03:03 -04:00
parent 0857dd0ae5
commit 91a6911a51
1 changed files with 9 additions and 13 deletions
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22
Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
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@ -772,19 +772,15 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Duplicate(SUBAw, ADDAw) StdCASE(ADDAw, perform_state_ = Perform_np_nn)
Duplicate(SUBAl, ADDAl) StdCASE(ADDAl, {
if(instruction_.mode(1) == Mode::AddressRegisterDirect) {
perform_state_ = Perform_np_nn;
} else {
switch(instruction_.mode(0)) {
default:
perform_state_ = Perform_np_n;
break;
case Mode::DataRegisterDirect:
case Mode::AddressRegisterDirect:
case Mode::ImmediateData:
perform_state_ = Perform_np_nn;
break;
}
switch(instruction_.mode(0)) {
default:
perform_state_ = Perform_np_n;
break;
case Mode::DataRegisterDirect:
case Mode::AddressRegisterDirect:
case Mode::ImmediateData:
perform_state_ = Perform_np_nn;
break;
}
})