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Adapted the Z80's perform_machine_cycle to return Cycles.

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This commit is contained in:
Thomas Harte 2017-07-25 22:25:44 -04:00
parent 279c369a1f
commit 966b5e6372
4 changed files with 10 additions and 10 deletions
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6
Machines/ZX8081/ZX8081.cpp
View File

@ -29,7 +29,7 @@ Machine::Machine() :
clear_all_keys();
}
int Machine::perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
Cycles Machine::perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
HalfCycles previous_counter = horizontal_counter_;
horizontal_counter_ += cycle.length;
@ -65,7 +65,7 @@ int Machine::perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
}
if(!cycle.is_terminal()) {
return 0;
return Cycles(0);
}
uint16_t address = cycle.address ? *cycle.address : 0;
@ -182,7 +182,7 @@ int Machine::perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
if(typer_) typer_->update(cycle.length.as_int());
return 0;
return Cycles(0);
}
void Machine::flush() {

2
Machines/ZX8081/ZX8081.hpp
View File

@ -47,7 +47,7 @@ class Machine:
public:
Machine();
int perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle);
Cycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle);
void flush();
void setup_output(float aspect_ratio);

6
Processors/Z80/Z80.hpp
View File

@ -888,7 +888,7 @@ template <class T> class Processor: public ClockReceiver<Processor<T>> {
while(bus_request_line_) {
static PartialMachineCycle bus_acknowledge_cycle = {PartialMachineCycle::BusAcknowledge, 1, nullptr, nullptr, false};
number_of_cycles_ -= Cycles(static_cast<T *>(this)->perform_machine_cycle(bus_acknowledge_cycle) + 1);
number_of_cycles_ -= static_cast<T *>(this)->perform_machine_cycle(bus_acknowledge_cycle) + Cycles(1);
if(!number_of_cycles_) {
static_cast<T *>(this)->flush();
return;
@ -1703,8 +1703,8 @@ template <class T> class Processor: public ClockReceiver<Processor<T>> {
*/
void flush() {}
int perform_machine_cycle(const PartialMachineCycle &cycle) {
return 0;
Cycles perform_machine_cycle(const PartialMachineCycle &cycle) {
return Cycles(0);
}
/*!

6
Processors/Z80/Z80AllRAM.cpp
View File

@ -16,10 +16,10 @@ class ConcreteAllRAMProcessor: public AllRAMProcessor, public Processor<Concrete
public:
ConcreteAllRAMProcessor() : AllRAMProcessor() {}
inline int perform_machine_cycle(const PartialMachineCycle &cycle) {
inline Cycles perform_machine_cycle(const PartialMachineCycle &cycle) {
timestamp_ += cycle.length.as_int();
if(!cycle.is_terminal()) {
return 0;
return Cycles(0);
}
uint16_t address = cycle.address ? *cycle.address : 0x0000;
@ -60,7 +60,7 @@ class ConcreteAllRAMProcessor: public AllRAMProcessor, public Processor<Concrete
delegate_->z80_all_ram_processor_did_perform_bus_operation(*this, cycle.operation, address, cycle.value ? *cycle.value : 0x00, timestamp_);
}
return 0;
return Cycles(0);
}
void run_for(const Cycles &cycles) {