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mirror of https://github.com/TomHarte/CLK.git synced 2025-01-11 08:30:55 +00:00

Eliminate phases due to lack of evidence.

This commit is contained in:
Thomas Harte 2024-10-09 11:59:27 -04:00
parent 7759fb7e68
commit 9acc80260f
4 changed files with 6 additions and 40 deletions

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@ -30,19 +30,7 @@ struct BusState {
class BusHandler { class BusHandler {
public: public:
/*! void perform_bus_cycle(const BusState &) {}
Performs the first phase of a 6845 bus cycle; this is the phase in which it is intended that
systems using the 6845 respect the bus state and produce pixels, sync or whatever they require.
*/
void perform_bus_cycle_phase1(const BusState &) {}
/*!
Performs the second phase of a 6845 bus cycle. Some bus state, including sync, is updated
directly after phase 1 and hence is visible to an observer during phase 2. Handlers may therefore
implement @c perform_bus_cycle_phase2 to be notified of the availability of that state without
having to wait until the next cycle has begun.
*/
void perform_bus_cycle_phase2(const BusState &) {}
}; };
enum class Personality { enum class Personality {
@ -196,10 +184,7 @@ template <class BusHandlerT, Personality personality, CursorType cursor_type> cl
bus_state_.cursor = is_cursor_line_ && bus_state_.cursor = is_cursor_line_ &&
bus_state_.refresh_address == layout_.cursor_address; bus_state_.refresh_address == layout_.cursor_address;
bus_state_.display_enable = character_is_visible_ && line_is_visible_; bus_state_.display_enable = character_is_visible_ && line_is_visible_;
bus_handler_.perform_bus_cycle(bus_state_);
// TODO: considate the two below.
perform_bus_cycle_phase1();
perform_bus_cycle_phase2();
// //
// Shared, stateless signals. // Shared, stateless signals.
@ -212,7 +197,7 @@ template <class BusHandlerT, Personality personality, CursorType cursor_type> cl
character_total_hit && was_eof && character_total_hit && was_eof &&
( (
layout_.interlace_mode_ == InterlaceMode::Off || layout_.interlace_mode_ == InterlaceMode::Off ||
!(bus_state_.field_count&1) !odd_field_
); );
// //
@ -373,17 +358,6 @@ template <class BusHandlerT, Personality personality, CursorType cursor_type> cl
private: private:
static constexpr uint16_t RefreshMask = (personality >= Personality::EGA) ? 0xffff : 0x3fff; static constexpr uint16_t RefreshMask = (personality >= Personality::EGA) ? 0xffff : 0x3fff;
inline void perform_bus_cycle_phase1() {
// Skew theory of operation: keep a history of the last three states, and apply whichever is selected.
// character_is_visible_shifter_ = (character_is_visible_shifter_ << 1) | unsigned(character_is_visible_);
// bus_state_.display_enable = (int(character_is_visible_shifter_) & display_skew_mask_) && line_is_visible_;
bus_handler_.perform_bus_cycle_phase1(bus_state_);
}
inline void perform_bus_cycle_phase2() {
bus_handler_.perform_bus_cycle_phase2(bus_state_);
}
BusHandlerT &bus_handler_; BusHandlerT &bus_handler_;
BusState bus_state_; BusState bus_state_;

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@ -189,7 +189,7 @@ class CRTCBusHandler {
The CRTC entry function for the main part of each clock cycle; takes the current The CRTC entry function for the main part of each clock cycle; takes the current
bus state and determines what output to produce based on the current palette and mode. bus state and determines what output to produce based on the current palette and mode.
*/ */
forceinline void perform_bus_cycle_phase1(const Motorola::CRTC::BusState &state) { forceinline void perform_bus_cycle(const Motorola::CRTC::BusState &state) {
// The gate array waits 2us to react to the CRTC's vsync signal, and then // The gate array waits 2us to react to the CRTC's vsync signal, and then
// caps output at 4us. Since the clock rate is 1Mhz, that's 2 and 4 cycles, // caps output at 4us. Since the clock rate is 1Mhz, that's 2 and 4 cycles,
// respectively. // respectively.
@ -299,13 +299,7 @@ class CRTCBusHandler {
} }
} }
} }
}
/*!
The CRTC entry function for phase 2 of each bus cycle, in which the next sync line state becomes
visible early. The CPC uses changes in sync to clock the interrupt timer.
*/
void perform_bus_cycle_phase2(const Motorola::CRTC::BusState &state) {
// Notify a leading hsync edge to the interrupt timer. // Notify a leading hsync edge to the interrupt timer.
// Per Interrupts in the CPC: "to be confirmed: does gate array count positive or negative edge transitions of HSYNC signal?"; // Per Interrupts in the CPC: "to be confirmed: does gate array count positive or negative edge transitions of HSYNC signal?";
// if you take it as given that display mode is latched as a result of hsync then Pipe Mania seems to imply that the count // if you take it as given that display mode is latched as a result of hsync then Pipe Mania seems to imply that the count

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@ -173,7 +173,7 @@ class CGA {
return new_state; return new_state;
} }
void perform_bus_cycle_phase1(const Motorola::CRTC::BusState &state) { void perform_bus_cycle(const Motorola::CRTC::BusState &state) {
// Determine new output state. // Determine new output state.
update_hsync(state.hsync); update_hsync(state.hsync);
const OutputState new_state = implied_state(state); const OutputState new_state = implied_state(state);
@ -246,7 +246,6 @@ class CGA {
count = 0; count = 0;
} }
} }
void perform_bus_cycle_phase2(const Motorola::CRTC::BusState &) {}
void flush_pixels() { void flush_pixels() {
crt.output_data(count * active_clock_divider, size_t((count * active_pixels_per_tick) / 8)); crt.output_data(count * active_clock_divider, size_t((count * active_pixels_per_tick) / 8));

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@ -104,7 +104,7 @@ class MDA {
return control_; return control_;
} }
void perform_bus_cycle_phase1(const Motorola::CRTC::BusState &state) { void perform_bus_cycle(const Motorola::CRTC::BusState &state) {
// Determine new output state. // Determine new output state.
const OutputState new_state = const OutputState new_state =
(state.hsync | state.vsync) ? OutputState::Sync : (state.hsync | state.vsync) ? OutputState::Sync :
@ -207,7 +207,6 @@ class MDA {
pixels = pixel_pointer = nullptr; pixels = pixel_pointer = nullptr;
} }
} }
void perform_bus_cycle_phase2(const Motorola::CRTC::BusState &) {}
Outputs::CRT::CRT crt; Outputs::CRT::CRT crt;