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Eliminate phases due to lack of evidence.
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7759fb7e68
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@ -30,19 +30,7 @@ struct BusState {
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class BusHandler {
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class BusHandler {
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public:
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public:
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/*!
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void perform_bus_cycle(const BusState &) {}
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Performs the first phase of a 6845 bus cycle; this is the phase in which it is intended that
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systems using the 6845 respect the bus state and produce pixels, sync or whatever they require.
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*/
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void perform_bus_cycle_phase1(const BusState &) {}
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/*!
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Performs the second phase of a 6845 bus cycle. Some bus state, including sync, is updated
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directly after phase 1 and hence is visible to an observer during phase 2. Handlers may therefore
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implement @c perform_bus_cycle_phase2 to be notified of the availability of that state without
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having to wait until the next cycle has begun.
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*/
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void perform_bus_cycle_phase2(const BusState &) {}
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};
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};
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enum class Personality {
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enum class Personality {
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@ -196,10 +184,7 @@ template <class BusHandlerT, Personality personality, CursorType cursor_type> cl
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bus_state_.cursor = is_cursor_line_ &&
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bus_state_.cursor = is_cursor_line_ &&
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bus_state_.refresh_address == layout_.cursor_address;
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bus_state_.refresh_address == layout_.cursor_address;
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bus_state_.display_enable = character_is_visible_ && line_is_visible_;
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bus_state_.display_enable = character_is_visible_ && line_is_visible_;
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bus_handler_.perform_bus_cycle(bus_state_);
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// TODO: considate the two below.
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perform_bus_cycle_phase1();
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perform_bus_cycle_phase2();
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//
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//
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// Shared, stateless signals.
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// Shared, stateless signals.
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@ -212,7 +197,7 @@ template <class BusHandlerT, Personality personality, CursorType cursor_type> cl
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character_total_hit && was_eof &&
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character_total_hit && was_eof &&
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(
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(
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layout_.interlace_mode_ == InterlaceMode::Off ||
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layout_.interlace_mode_ == InterlaceMode::Off ||
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!(bus_state_.field_count&1)
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!odd_field_
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);
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);
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//
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//
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@ -373,17 +358,6 @@ template <class BusHandlerT, Personality personality, CursorType cursor_type> cl
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private:
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private:
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static constexpr uint16_t RefreshMask = (personality >= Personality::EGA) ? 0xffff : 0x3fff;
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static constexpr uint16_t RefreshMask = (personality >= Personality::EGA) ? 0xffff : 0x3fff;
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inline void perform_bus_cycle_phase1() {
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// Skew theory of operation: keep a history of the last three states, and apply whichever is selected.
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// character_is_visible_shifter_ = (character_is_visible_shifter_ << 1) | unsigned(character_is_visible_);
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// bus_state_.display_enable = (int(character_is_visible_shifter_) & display_skew_mask_) && line_is_visible_;
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bus_handler_.perform_bus_cycle_phase1(bus_state_);
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}
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inline void perform_bus_cycle_phase2() {
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bus_handler_.perform_bus_cycle_phase2(bus_state_);
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}
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BusHandlerT &bus_handler_;
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BusHandlerT &bus_handler_;
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BusState bus_state_;
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BusState bus_state_;
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@ -189,7 +189,7 @@ class CRTCBusHandler {
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The CRTC entry function for the main part of each clock cycle; takes the current
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The CRTC entry function for the main part of each clock cycle; takes the current
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bus state and determines what output to produce based on the current palette and mode.
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bus state and determines what output to produce based on the current palette and mode.
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*/
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*/
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forceinline void perform_bus_cycle_phase1(const Motorola::CRTC::BusState &state) {
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forceinline void perform_bus_cycle(const Motorola::CRTC::BusState &state) {
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// The gate array waits 2us to react to the CRTC's vsync signal, and then
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// The gate array waits 2us to react to the CRTC's vsync signal, and then
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// caps output at 4us. Since the clock rate is 1Mhz, that's 2 and 4 cycles,
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// caps output at 4us. Since the clock rate is 1Mhz, that's 2 and 4 cycles,
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// respectively.
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// respectively.
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@ -299,13 +299,7 @@ class CRTCBusHandler {
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}
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}
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}
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}
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}
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}
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}
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/*!
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The CRTC entry function for phase 2 of each bus cycle, in which the next sync line state becomes
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visible early. The CPC uses changes in sync to clock the interrupt timer.
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*/
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void perform_bus_cycle_phase2(const Motorola::CRTC::BusState &state) {
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// Notify a leading hsync edge to the interrupt timer.
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// Notify a leading hsync edge to the interrupt timer.
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// Per Interrupts in the CPC: "to be confirmed: does gate array count positive or negative edge transitions of HSYNC signal?";
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// Per Interrupts in the CPC: "to be confirmed: does gate array count positive or negative edge transitions of HSYNC signal?";
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// if you take it as given that display mode is latched as a result of hsync then Pipe Mania seems to imply that the count
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// if you take it as given that display mode is latched as a result of hsync then Pipe Mania seems to imply that the count
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@ -173,7 +173,7 @@ class CGA {
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return new_state;
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return new_state;
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}
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}
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void perform_bus_cycle_phase1(const Motorola::CRTC::BusState &state) {
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void perform_bus_cycle(const Motorola::CRTC::BusState &state) {
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// Determine new output state.
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// Determine new output state.
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update_hsync(state.hsync);
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update_hsync(state.hsync);
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const OutputState new_state = implied_state(state);
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const OutputState new_state = implied_state(state);
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@ -246,7 +246,6 @@ class CGA {
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count = 0;
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count = 0;
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}
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}
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}
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}
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void perform_bus_cycle_phase2(const Motorola::CRTC::BusState &) {}
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void flush_pixels() {
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void flush_pixels() {
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crt.output_data(count * active_clock_divider, size_t((count * active_pixels_per_tick) / 8));
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crt.output_data(count * active_clock_divider, size_t((count * active_pixels_per_tick) / 8));
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@ -104,7 +104,7 @@ class MDA {
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return control_;
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return control_;
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}
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}
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void perform_bus_cycle_phase1(const Motorola::CRTC::BusState &state) {
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void perform_bus_cycle(const Motorola::CRTC::BusState &state) {
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// Determine new output state.
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// Determine new output state.
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const OutputState new_state =
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const OutputState new_state =
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(state.hsync | state.vsync) ? OutputState::Sync :
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(state.hsync | state.vsync) ? OutputState::Sync :
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@ -207,7 +207,6 @@ class MDA {
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pixels = pixel_pointer = nullptr;
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pixels = pixel_pointer = nullptr;
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}
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}
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}
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}
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void perform_bus_cycle_phase2(const Motorola::CRTC::BusState &) {}
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Outputs::CRT::CRT crt;
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Outputs::CRT::CRT crt;
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