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Add MOVEA, be slightly more careful about next_operand_.

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Thomas Harte 2022-05-24 11:30:09 -04:00
parent 4b07c41df9
commit a7e8aef9d3
2 changed files with 11 additions and 8 deletions
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13
Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
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@ -20,7 +20,7 @@ namespace MC68000Mk2 {
// TODO: BERR, interrupt inputs, etc; and obeying the trace flag. // TODO: BERR, interrupt inputs, etc; and obeying the trace flag.
// Also, from Instruction.hpp: // Also, from Instruction.hpp:
// //
// MOVEAw, MOVEAl // TRAP, TRAPV
// //
// Not provided by a 68000: Bccl, BSRl // Not provided by a 68000: Bccl, BSRl
@ -585,7 +585,9 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
StdCASE(EXTwtol, perform_state_ = Perform_np); StdCASE(EXTwtol, perform_state_ = Perform_np);
StdCASE(MOVEb, perform_state_ = MOVE); StdCASE(MOVEb, perform_state_ = MOVE);
Duplicate(MOVEAw, MOVEw)
StdCASE(MOVEw, perform_state_ = MOVE); StdCASE(MOVEw, perform_state_ = MOVE);
Duplicate(MOVEAl, MOVEl)
StdCASE(MOVEl, perform_state_ = MOVE); StdCASE(MOVEl, perform_state_ = MOVE);
StdCASE(CMPb, perform_state_ = Perform_np); StdCASE(CMPb, perform_state_ = Perform_np);
@ -814,12 +816,10 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
StdCASE(LEA, { StdCASE(LEA, {
post_ea_state_ = LEA; post_ea_state_ = LEA;
next_operand_ = 0;
MoveToStateSpecific(CalcEffectiveAddress); MoveToStateSpecific(CalcEffectiveAddress);
}); });
StdCASE(PEA, { StdCASE(PEA, {
post_ea_state_ = PEA; post_ea_state_ = PEA;
next_operand_ = 0;
MoveToStateSpecific(CalcEffectiveAddress); MoveToStateSpecific(CalcEffectiveAddress);
}); });
@ -830,7 +830,6 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
// for the other cases. // for the other cases.
if(instruction_.mode(0) != Mode::DataRegisterDirect) { if(instruction_.mode(0) != Mode::DataRegisterDirect) {
post_ea_state_ = TAS; post_ea_state_ = TAS;
next_operand_ = 0;
MoveToStateSpecific(CalcEffectiveAddress); MoveToStateSpecific(CalcEffectiveAddress);
} }
@ -1440,8 +1439,12 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
// Various generic forms of perform. // Various generic forms of perform.
// //
#define MoveToWritePhase() \ #define MoveToWritePhase() \
if(operand_flags_ & 0x0c) { \
next_operand_ = 0; \ next_operand_ = 0; \
if(operand_flags_ & 0x0c) MoveToStateSpecific(StoreOperand) else MoveToStateSpecific(Decode) MoveToStateSpecific(StoreOperand); \
} else { \
MoveToStateSpecific(Decode); \
}
BeginState(Perform_np): BeginState(Perform_np):
PerformDynamic(); PerformDynamic();

2
Processors/68000Mk2/Implementation/68000Mk2Storage.hpp
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@ -87,7 +87,7 @@ struct ProcessorBase: public InstructionSet::M68k::NullFlowController {
/// When fetching or storing operands, this is the next one to fetch /// When fetching or storing operands, this is the next one to fetch
/// or store. /// or store.
int next_operand_ = 0; int next_operand_ = -1;
/// Storage for a temporary address, which can't be a local because it'll /// Storage for a temporary address, which can't be a local because it'll
/// be used to populate microcycles, which may persist beyond an entry /// be used to populate microcycles, which may persist beyond an entry