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Add missing validations.

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This commit is contained in:
Thomas Harte 2022-04-08 09:47:04 -04:00
parent 1f44ad1723
commit aac2f7dd73
1 changed files with 24 additions and 5 deletions
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29
InstructionSets/PowerPC/Decoder.cpp
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@ -21,6 +21,8 @@ template <Model model, bool validate_reserved_bits, Operation operation> Instruc
// Otherwise, validation depends on operation
// (and, in principle, processor model).
switch(operation) {
case Operation::absx: case Operation::clcs:
case Operation::nabsx:
case Operation::addmex: case Operation::addzex:
case Operation::bcctrx: case Operation::bclrx:
case Operation::cntlzdx: case Operation::cntlzwx:
@ -143,10 +145,18 @@ template <Model model, bool validate_reserved_bits, Operation operation> Instruc
if(opcode & 0b000000'00000'10000'11111'0000000000'1) return Instruction(opcode);
break;
case Operation::mtsrin:
case Operation::mtsrin: case Operation::mfsrin:
if(opcode & 0b000000'00000'11111'00000'0000000000'1) return Instruction(opcode);
break;
case Operation::mfsr:
if(opcode & 0b000000'00000'10000'11111'0000000000'1) return Instruction(opcode);
break;
case Operation::mtcrf:
if(opcode & 0b000000'00000'10000'00001'0000000000'1) return Instruction(opcode);
break;
case Operation::mulhdx: case Operation::mulhdux:
case Operation::mulhwx: case Operation::mulhwux:
if(opcode & 0b000000'00000'00000'00000'1000000000'0) return Instruction(opcode);
@ -165,10 +175,19 @@ template <Model model, bool validate_reserved_bits, Operation operation> Instruc
if(!(opcode & 0b000000'00000'00000'00000'0000000000'1)) return Instruction(opcode);
break;
case Operation::clcs:
if(opcode & 0b000000'00000'00000'11111'0000000000'1) return Instruction(opcode);
break;
case Operation::divx: case Operation::divsx:
case Operation::dozx: case Operation::dozi:
case Operation::lscbxx:
case Operation::maskgx: case Operation::maskirx:
case Operation::mulx:
case Operation::rlmix: case Operation::rribx:
case Operation::slex: case Operation::sleqx: case Operation::sliqx:
case Operation::slliqx: case Operation::sllqx: case Operation::slqx:
case Operation::sraiqx: case Operation::sraqx:
case Operation::srex: case Operation::sreqx:
case Operation::sriqx: case Operation::srliqx:
case Operation::srlqx: case Operation::srqx:
case Operation::sreax:
case Operation::addx: case Operation::addcx: case Operation::addex:
case Operation::addi: case Operation::addic: case Operation::addic_:
case Operation::addis: