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https://github.com/TomHarte/CLK.git
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Adds empty callouts for all serial port registers.
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@ -885,10 +885,9 @@ void Chipset::write(uint32_t address, uint16_t value, bool allow_conversion) {
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// Serial port.
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case 0x030: // SERDAT
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LOG("TODO: serial data: " << PADHEX(4) << value);
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serial_.set_data(value);
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break;
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case 0x032: // SERPER
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LOG("TODO: serial control: " << PADHEX(4) << value);
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serial_.set_control(value);
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break;
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@ -1133,9 +1132,7 @@ uint16_t Chipset::read(uint32_t address, bool allow_conversion) {
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return 0xffff;
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// Serial port.
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case 0x018: // SERDATR
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LOG("TODO: serial data and status");
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return 0x3000; // i.e. transmit buffer empty.
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case 0x018: return serial_.get_status();
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// DMA management.
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case 0x002: return dma_control_ | blitter_.get_status(); // DMACONR
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@ -1253,3 +1250,15 @@ void Chipset::set_component_prefers_clocking(ClockingHint::Source *, ClockingHin
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void Chipset::flush() {
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}
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// MARK: - Serial port.
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void Chipset::SerialPort::set_control(uint16_t) {
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}
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void Chipset::SerialPort::set_data(uint16_t) {
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}
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uint16_t Chipset::SerialPort::get_status() {
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return 0x3000;
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}
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@ -208,7 +208,9 @@ class Chipset: private ClockingHint::Observer {
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class SerialPort {
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public:
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void set_control(uint16_t) {}
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void set_control(uint16_t);
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void set_data(uint16_t);
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uint16_t get_status();
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private:
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uint16_t value = 0, reload = 0;
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