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Refactors the Z80 to separate out interface and implementation.
Following the pattern just established by the 6502, puts all implementation specifics beyond the visibility of a human reading Z80.hpp and in subfolders so as to promote the idea that they shouldn't go out of their way.
This commit is contained in:
Thomas Harte
223
Processors/Z80/Implementation/Z80Base.cpp
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223
Processors/Z80/Implementation/Z80Base.cpp
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//
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// Z80Storage.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 01/09/2017.
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// Copyright © 2017 Thomas Harte. All rights reserved.
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//
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#include "../Z80.hpp"
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using namespace CPU::Z80;
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ProcessorStorage::ProcessorStorage() :
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halt_mask_(0xff),
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interrupt_mode_(0),
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wait_line_(false),
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request_status_(Interrupt::PowerOn),
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last_request_status_(Interrupt::PowerOn),
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irq_line_(false),
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nmi_line_(false),
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bus_request_line_(false),
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pc_increment_(1),
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scheduled_program_counter_(nullptr) {
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set_flags(0xff);
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}
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void ProcessorStorage::install_default_instruction_set() {
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MicroOp conditional_call_untaken_program[] = Sequence(ReadInc(pc_, temp16_.bytes.high));
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copy_program(conditional_call_untaken_program, conditional_call_untaken_program_);
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assemble_base_page(base_page_, hl_, false, cb_page_);
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assemble_base_page(dd_page_, ix_, true, ddcb_page_);
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assemble_base_page(fd_page_, iy_, true, fdcb_page_);
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assemble_ed_page(ed_page_);
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fdcb_page_.r_step = 0;
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fd_page_.is_indexed = true;
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fdcb_page_.is_indexed = true;
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ddcb_page_.r_step = 0;
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dd_page_.is_indexed = true;
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ddcb_page_.is_indexed = true;
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assemble_fetch_decode_execute(base_page_, 4);
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assemble_fetch_decode_execute(dd_page_, 4);
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assemble_fetch_decode_execute(fd_page_, 4);
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assemble_fetch_decode_execute(ed_page_, 4);
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assemble_fetch_decode_execute(cb_page_, 4);
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assemble_fetch_decode_execute(fdcb_page_, 3);
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assemble_fetch_decode_execute(ddcb_page_, 3);
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MicroOp reset_program[] = Sequence(InternalOperation(6), {MicroOp::Reset});
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// Justification for NMI timing: per Wilf Rigter on the ZX81 (http://www.user.dccnet.com/wrigter/index_files/ZX81WAIT.htm),
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// wait cycles occur between T2 and T3 during NMI; extending the refresh cycle is also consistent with my guess
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// for the action of other non-four-cycle opcode fetches
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MicroOp nmi_program[] = {
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{ MicroOp::BeginNMI },
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BusOp(ReadOpcodeStart()),
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BusOp(ReadOpcodeWait(true)),
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BusOp(ReadOpcodeEnd()),
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BusOp(Refresh(6)),
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Push(pc_),
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{ MicroOp::JumpTo66, nullptr, nullptr},
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{ MicroOp::MoveToNextProgram }
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};
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MicroOp irq_mode0_program[] = {
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{ MicroOp::BeginIRQMode0 },
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BusOp(IntAckStart(5, operation_)),
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BusOp(IntWait(operation_)),
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BusOp(IntAckEnd(operation_)),
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{ MicroOp::DecodeOperationNoRChange }
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};
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MicroOp irq_mode1_program[] = {
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{ MicroOp::BeginIRQ },
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BusOp(IntAckStart(7, operation_)), // 7 half cycles (including +
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BusOp(IntWait(operation_)), // [potentially 2 half cycles] +
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BusOp(IntAckEnd(operation_)), // Implicitly 3 half cycles +
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BusOp(Refresh(4)), // 4 half cycles +
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Push(pc_), // 12 half cycles = 26 half cycles = 13 cycles
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{ MicroOp::Move16, &temp16_.full, &pc_.full },
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{ MicroOp::MoveToNextProgram }
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};
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MicroOp irq_mode2_program[] = {
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{ MicroOp::BeginIRQ },
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BusOp(IntAckStart(7, temp16_.bytes.low)),
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BusOp(IntWait(temp16_.bytes.low)),
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BusOp(IntAckEnd(temp16_.bytes.low)),
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BusOp(Refresh(4)),
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Push(pc_),
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{ MicroOp::Move8, &ir_.bytes.high, &temp16_.bytes.high },
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Read16(temp16_, pc_),
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{ MicroOp::MoveToNextProgram }
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};
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copy_program(reset_program, reset_program_);
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copy_program(nmi_program, nmi_program_);
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copy_program(irq_mode0_program, irq_program_[0]);
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copy_program(irq_mode1_program, irq_program_[1]);
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copy_program(irq_mode2_program, irq_program_[2]);
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}
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void ProcessorBase::reset_power_on() {
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request_status_ &= ~Interrupt::PowerOn;
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last_request_status_ &= ~Interrupt::PowerOn;
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}
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uint16_t ProcessorBase::get_value_of_register(Register r) {
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switch (r) {
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case Register::ProgramCounter: return pc_.full;
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case Register::StackPointer: return sp_.full;
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case Register::A: return a_;
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case Register::Flags: return get_flags();
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case Register::AF: return (uint16_t)((a_ << 8) | get_flags());
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case Register::B: return bc_.bytes.high;
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case Register::C: return bc_.bytes.low;
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case Register::BC: return bc_.full;
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case Register::D: return de_.bytes.high;
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case Register::E: return de_.bytes.low;
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case Register::DE: return de_.full;
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case Register::H: return hl_.bytes.high;
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case Register::L: return hl_.bytes.low;
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case Register::HL: return hl_.full;
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case Register::ADash: return afDash_.bytes.high;
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case Register::FlagsDash: return afDash_.bytes.low;
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case Register::AFDash: return afDash_.full;
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case Register::BDash: return bcDash_.bytes.high;
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case Register::CDash: return bcDash_.bytes.low;
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case Register::BCDash: return bcDash_.full;
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case Register::DDash: return deDash_.bytes.high;
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case Register::EDash: return deDash_.bytes.low;
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case Register::DEDash: return deDash_.full;
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case Register::HDash: return hlDash_.bytes.high;
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case Register::LDash: return hlDash_.bytes.low;
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case Register::HLDash: return hlDash_.full;
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case Register::IXh: return ix_.bytes.high;
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case Register::IXl: return ix_.bytes.low;
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case Register::IX: return ix_.full;
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case Register::IYh: return iy_.bytes.high;
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case Register::IYl: return iy_.bytes.low;
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case Register::IY: return iy_.full;
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case Register::R: return ir_.bytes.low;
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case Register::I: return ir_.bytes.high;
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case Register::Refresh: return ir_.full;
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case Register::IFF1: return iff1_ ? 1 : 0;
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case Register::IFF2: return iff2_ ? 1 : 0;
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case Register::IM: return (uint16_t)interrupt_mode_;
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case Register::MemPtr: return memptr_.full;
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default: return 0;
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}
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}
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void ProcessorBase::set_value_of_register(Register r, uint16_t value) {
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switch (r) {
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case Register::ProgramCounter: pc_.full = value; break;
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case Register::StackPointer: sp_.full = value; break;
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case Register::A: a_ = (uint8_t)value; break;
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case Register::AF: a_ = (uint8_t)(value >> 8); // deliberate fallthrough...
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case Register::Flags: set_flags((uint8_t)value); break;
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case Register::B: bc_.bytes.high = (uint8_t)value; break;
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case Register::C: bc_.bytes.low = (uint8_t)value; break;
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case Register::BC: bc_.full = value; break;
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case Register::D: de_.bytes.high = (uint8_t)value; break;
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case Register::E: de_.bytes.low = (uint8_t)value; break;
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case Register::DE: de_.full = value; break;
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case Register::H: hl_.bytes.high = (uint8_t)value; break;
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case Register::L: hl_.bytes.low = (uint8_t)value; break;
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case Register::HL: hl_.full = value; break;
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case Register::ADash: afDash_.bytes.high = (uint8_t)value; break;
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case Register::FlagsDash: afDash_.bytes.low = (uint8_t)value; break;
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case Register::AFDash: afDash_.full = value; break;
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case Register::BDash: bcDash_.bytes.high = (uint8_t)value; break;
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case Register::CDash: bcDash_.bytes.low = (uint8_t)value; break;
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case Register::BCDash: bcDash_.full = value; break;
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case Register::DDash: deDash_.bytes.high = (uint8_t)value; break;
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case Register::EDash: deDash_.bytes.low = (uint8_t)value; break;
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case Register::DEDash: deDash_.full = value; break;
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case Register::HDash: hlDash_.bytes.high = (uint8_t)value; break;
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case Register::LDash: hlDash_.bytes.low = (uint8_t)value; break;
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case Register::HLDash: hlDash_.full = value; break;
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case Register::IXh: ix_.bytes.high = (uint8_t)value; break;
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case Register::IXl: ix_.bytes.low = (uint8_t)value; break;
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case Register::IX: ix_.full = value; break;
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case Register::IYh: iy_.bytes.high = (uint8_t)value; break;
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case Register::IYl: iy_.bytes.low = (uint8_t)value; break;
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case Register::IY: iy_.full = value; break;
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case Register::R: ir_.bytes.low = (uint8_t)value; break;
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case Register::I: ir_.bytes.high = (uint8_t)value; break;
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case Register::Refresh: ir_.full = (uint16_t)value; break;
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case Register::IFF1: iff1_ = !!value; break;
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case Register::IFF2: iff2_ = !!value; break;
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case Register::IM: interrupt_mode_ = value % 3; break;
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case Register::MemPtr: memptr_.full = value; break;
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default: break;
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}
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}
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PartialMachineCycle::PartialMachineCycle(const PartialMachineCycle &rhs) :
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operation(rhs.operation),
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length(rhs.length),
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address(rhs.address),
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value(rhs.value),
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was_requested(rhs.was_requested) {}
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PartialMachineCycle::PartialMachineCycle(Operation operation, HalfCycles length, uint16_t *address, uint8_t *value, bool was_requested) noexcept :
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operation(operation), length(length), address(address), value(value), was_requested(was_requested) {}
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PartialMachineCycle::PartialMachineCycle() noexcept :
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operation(Internal), length(0), address(nullptr), value(nullptr), was_requested(false) {}
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