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https://github.com/TomHarte/CLK.git
synced 2025-02-03 22:33:29 +00:00
Blocks off the AY from inputs in 48kb mode.
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f5c7746493
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@ -211,21 +211,43 @@ template<Model model> class ConcreteMachine:
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// Apply contention if necessary.
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if constexpr (model >= Model::Plus2a) {
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// Model applied: the trigger for the ULA inserting a delay is the falling edge
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// of MREQ, which is always half a cycle into a read or write.
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if(
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is_contended_[address >> 14] &&
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cycle.operation >= PartialMachineCycle::ReadOpcodeStart &&
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cycle.operation <= PartialMachineCycle::WriteStart) {
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// Assumption here: the trigger for the ULA inserting a delay is the falling edge
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// of MREQ, which is always half a cycle into a read or write.
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//
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// TODO: somehow provide that information in the PartialMachineCycle?
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const HalfCycles delay = video_.last_valid()->access_delay(video_.time_since_flush() + HalfCycles(1));
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advance(cycle.length + delay);
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return delay;
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}
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} else {
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// TODO.
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switch(cycle.operation) {
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default:
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advance(cycle.length);
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return HalfCycles(0);
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case PartialMachineCycle::ReadOpcodeStart:
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case PartialMachineCycle::ReadStart:
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case PartialMachineCycle::WriteStart:
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break;
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case CPU::Z80::PartialMachineCycle::InputStart:
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case CPU::Z80::PartialMachineCycle::OutputStart:
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break;
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case PartialMachineCycle::Internal:
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break;
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case CPU::Z80::PartialMachineCycle::Input:
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case CPU::Z80::PartialMachineCycle::Output:
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case CPU::Z80::PartialMachineCycle::Read:
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case CPU::Z80::PartialMachineCycle::Write:
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case CPU::Z80::PartialMachineCycle::ReadOpcode:
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// For these, carry on into the actual handler, below.
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break;
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}
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}
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// For all other machine cycles, model the action as happening at the end of the machine cycle;
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@ -315,6 +337,7 @@ template<Model model> class ConcreteMachine:
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}
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}
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// Route to the AY if one is fitted.
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if constexpr (model >= Model::OneTwoEightK) {
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if((address & 0xc002) == 0xc000) {
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// Select AY register.
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@ -329,6 +352,7 @@ template<Model model> class ConcreteMachine:
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}
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}
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// Check for FDC accesses.
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if constexpr (model == Model::Plus3) {
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switch(address) {
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default: break;
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@ -370,17 +394,21 @@ template<Model model> class ConcreteMachine:
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}
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}
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if((address & 0xc002) == 0xc000) {
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// Read from AY register.
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update_audio();
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*cycle.value &= GI::AY38910::Utility::read(ay_);
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if constexpr (model >= Model::OneTwoEightK) {
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if((address & 0xc002) == 0xc000) {
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// Read from AY register.
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update_audio();
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*cycle.value &= GI::AY38910::Utility::read(ay_);
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}
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}
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// Check for a floating bus read; these are particularly arcane
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// on the +2a/+3. See footnote to https://spectrumforeveryone.com/technical/memory-contention-floating-bus/
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// and, much more rigorously, http://sky.relative-path.com/zx/floating_bus.html
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if(!disable_paging_ && (address & 0xf003) == 0x0001) {
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*cycle.value &= video_->get_floating_value();
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if constexpr (model >= Model::Plus2a) {
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// Check for a +2a/+3 floating bus read; these are particularly arcane.
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// See footnote to https://spectrumforeveryone.com/technical/memory-contention-floating-bus/
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// and, much more rigorously, http://sky.relative-path.com/zx/floating_bus.html
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if(!disable_paging_ && (address & 0xf003) == 0x0001) {
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*cycle.value &= video_->get_floating_value();
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}
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}
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if constexpr (model == Model::Plus3) {
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