6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-23 03:32:32 +00:00
Code Issues Projects Releases Wiki Activity

Fixing the OUT repetition group reduces the code to one failing test.

Browse Source
This commit is contained in:
Thomas Harte 2017-05-29 10:48:53 -04:00
parent a47b339668
commit b67331e018
2 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
OSBindings/Mac/Clock SignalTests/FUSETests.swift
View File

@ -167,7 +167,7 @@ class FUSETests: XCTestCase {
let name = itemDictionary["name"] as! String
// if name != "eda2" {
// if name != "eda3" {
// continue;
// }
@ -194,7 +194,7 @@ class FUSETests: XCTestCase {
let finalState = RegisterState(machine: machine)
XCTAssert(finalState == targetState, "Failed \(name)")
XCTAssertEqual(finalState, targetState, "Failed \(name)")
// if finalState != targetState {
// failures = failures + 1
// if failures == 5 {

8
Processors/Z80/Z80.hpp
View File

@ -390,22 +390,22 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
/* 0xa0 LDI */ Program(FETCHL(temp8_, hl_), STOREL(temp8_, de_), WAIT(2), {MicroOp::LDI}),
/* 0xa1 CPI */ Program(FETCHL(temp8_, hl_), WAIT(5), {MicroOp::CPI}),
/* 0xa2 INI */ Program(IN(bc_, temp8_), STOREL(temp8_, hl_), WAIT(1), {MicroOp::INI}),
/* 0xa3 OTI */ Program(OUT(bc_, temp8_), STOREL(temp8_, hl_), WAIT(1), {MicroOp::OUTI}),
/* 0xa3 OTI */ Program(FETCHL(temp8_, hl_), OUT(bc_, temp8_), WAIT(1), {MicroOp::OUTI}),
XX, XX, XX, XX,
/* 0xa8 LDD */ Program(FETCHL(temp8_, hl_), STOREL(temp8_, de_), WAIT(2), {MicroOp::LDD}),
/* 0xa9 CPD */ Program(FETCHL(temp8_, hl_), WAIT(5), {MicroOp::CPD}),
/* 0xaa IND */ Program(IN(bc_, temp8_), STOREL(temp8_, hl_), WAIT(1), {MicroOp::IND}),
/* 0xab OTD */ Program(OUT(bc_, temp8_), STOREL(temp8_, hl_), WAIT(1), {MicroOp::OUTD}),
/* 0xab OTD */ Program(FETCHL(temp8_, hl_), OUT(bc_, temp8_), WAIT(1), {MicroOp::OUTD}),
XX, XX, XX, XX,
/* 0xb0 LDIR */ Program(FETCHL(temp8_, hl_), STOREL(temp8_, de_), WAIT(2), {MicroOp::LDIR}, WAIT(5)),
/* 0xb1 CPIR */ Program(FETCHL(temp8_, hl_), WAIT(5), {MicroOp::CPIR}, WAIT(5)),
/* 0xb2 INIR */ Program(IN(bc_, temp8_), STOREL(temp8_, hl_), WAIT(1), {MicroOp::INIR}, WAIT(5)),
/* 0xb3 OTIR */ Program(IN(bc_, temp8_), STOREL(temp8_, hl_), WAIT(1), {MicroOp::OUTIR}, WAIT(5)),
/* 0xb3 OTIR */ Program(FETCHL(temp8_, hl_), OUT(bc_, temp8_), WAIT(1), {MicroOp::OUTIR}, WAIT(5)),
XX, XX, XX, XX,
/* 0xb8 LDDR */ Program(FETCHL(temp8_, hl_), STOREL(temp8_, de_), WAIT(2), {MicroOp::LDDR}, WAIT(5)),
/* 0xb9 CPDR */ Program(FETCHL(temp8_, hl_), WAIT(5), {MicroOp::CPDR}, WAIT(5)),
/* 0xba INDR */ Program(IN(bc_, temp8_), STOREL(temp8_, hl_), WAIT(1), {MicroOp::INDR}, WAIT(5)),
/* 0xbb OTDR */ Program(IN(bc_, temp8_), STOREL(temp8_, hl_), WAIT(1), {MicroOp::OUTDR}, WAIT(5)),
/* 0xbb OTDR */ Program(FETCHL(temp8_, hl_), OUT(bc_, temp8_), WAIT(1), {MicroOp::OUTDR}, WAIT(5)),
XX, XX, XX, XX,
NOP_ROW(), /* 0xc0 */
NOP_ROW(), /* 0xd0 */