1
0
mirror of https://github.com/TomHarte/CLK.git synced 2024-07-11 04:28:58 +00:00

Merge pull request #591 from TomHarte/ColecoVisionM1

Adds a single-cycle M1 delay to the ColecoVision.
This commit is contained in:
Thomas Harte 2019-02-27 22:02:58 -05:00 committed by GitHub
commit b81e59fd8f
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23

View File

@ -192,14 +192,14 @@ class ConcreteMachine:
// MARK: Z80::BusHandler
forceinline HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
// The SN76489 will use its ready line to trigger the Z80's wait for three
// cycles when accessed. Everything else runs at full speed. Short-circuit
// cycles when accessed. M1 cycles are extended by a single cycle. Short-circuit
// that whole piece of communications by just accruing the time here if applicable.
const HalfCycles penalty(
(
cycle.operation == CPU::Z80::PartialMachineCycle::Output &&
((*cycle.address >> 5) & 7) == 7
) ? 6 : 0
);
HalfCycles penalty(0);
if(cycle.operation == CPU::Z80::PartialMachineCycle::Output && ((*cycle.address >> 5) & 7) == 7) {
penalty = HalfCycles(6);
} else if(cycle.operation == CPU::Z80::PartialMachineCycle::ReadOpcode) {
penalty = HalfCycles(2);
}
const HalfCycles length = cycle.length + penalty;
time_since_vdp_update_ += length;