6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-09-27 18:55:48 +00:00
Code Issues Projects Releases Wiki Activity

Adds a single-cycle M1 delay to the ColecoVision.

Browse Source
This commit is contained in:
Thomas Harte 2019-02-27 22:01:30 -05:00
parent 28e69152d8
commit d2da55aa03
1 changed files with 7 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
Machines/ColecoVision/ColecoVision.cpp
View File

@ -192,14 +192,14 @@ class ConcreteMachine:
// MARK: Z80::BusHandler
forceinline HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
// The SN76489 will use its ready line to trigger the Z80's wait for three
// cycles when accessed. Everything else runs at full speed. Short-circuit
// cycles when accessed. M1 cycles are extended by a single cycle. Short-circuit
// that whole piece of communications by just accruing the time here if applicable.
const HalfCycles penalty(
(
cycle.operation == CPU::Z80::PartialMachineCycle::Output &&
((*cycle.address >> 5) & 7) == 7
) ? 6 : 0
);
HalfCycles penalty(0);
if(cycle.operation == CPU::Z80::PartialMachineCycle::Output && ((*cycle.address >> 5) & 7) == 7) {
penalty = HalfCycles(6);
} else if(cycle.operation == CPU::Z80::PartialMachineCycle::ReadOpcode) {
penalty = HalfCycles(2);
}
const HalfCycles length = cycle.length + penalty;
time_since_vdp_update_ += length;