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mirror of https://github.com/TomHarte/CLK.git synced 2025-02-03 07:33:29 +00:00

Improves logging further.

To investigate the new perpetual loop.
This commit is contained in:
Thomas Harte 2021-07-26 17:02:30 -04:00
parent 87dcd82f69
commit bcb7bb5cce
4 changed files with 32 additions and 14 deletions

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@ -263,6 +263,8 @@ void MOS6526<BusHandlerT, personality>::run_for(const HalfCycles half_cycles) {
template <typename BusHandlerT, Personality personality> template <typename BusHandlerT, Personality personality>
void MOS6526<BusHandlerT, personality>::advance_tod(int count) { void MOS6526<BusHandlerT, personality>::advance_tod(int count) {
if(!count) return;
if constexpr(personality == Personality::P8250) { if constexpr(personality == Personality::P8250) {
// The 8250 uses a simple binary counter to replace the // The 8250 uses a simple binary counter to replace the
// 6526's time-of-day clock. So this is easy. // 6526's time-of-day clock. So this is easy.

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@ -30,15 +30,17 @@ struct MOS6526Storage {
uint16_t reload = 0; uint16_t reload = 0;
uint16_t value = 0; uint16_t value = 0;
uint8_t control = 0; uint8_t control = 0;
bool is_counting = false;
template <int shift> void set_reload(uint8_t v) { template <int shift> void set_reload(uint8_t v) {
reload = (reload & (0xff00 >> shift)) | uint16_t(v << shift); reload = (reload & (0xff00 >> shift)) | uint16_t(v << shift);
if constexpr (shift == 8) { if constexpr (shift == 8) {
if(!is_counting) { if(!(control&1)) {
is_counting = true;
value = reload; value = reload;
if(control&8) {
control |= 1; // At a guess: start one-shot automatically (?)
}
} }
} }
} }
@ -48,20 +50,22 @@ struct MOS6526Storage {
if(v & 0x10) { if(v & 0x10) {
value = reload; value = reload;
} }
is_counting |= (v & 0x18) == 0x10;
// Force reload + one-shot => start counting (?)
if((v & 0x18) == 0x18) {
control |= 1;
}
} }
int subtract(int count) { int subtract(int count) {
if(control & 8) { if(control & 8) {
// One-shot. // One-shot.
if(is_counting) { if(value < count) {
if(value < count) { value = reload;
value = reload; control &= 0xfe;
is_counting = false; return 1;
return 1; } else {
} else { value -= count;
value -= count;
}
} }
return 0; return 0;
} else { } else {

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@ -124,7 +124,7 @@ class ConcreteMachine:
// directly to the chip enables. // directly to the chip enables.
if((address & 0xe0'0000) == 0xa0'0000) { if((address & 0xe0'0000) == 0xa0'0000) {
const int reg = address >> 8; const int reg = address >> 8;
LOG("CIA access: " << PADHEX(4) << *cycle.address); LOG("CIA " << (cycle.operation & Microcycle::Read ? "read " : "write ") << PADHEX(4) << *cycle.address);
if(cycle.operation & Microcycle::Read) { if(cycle.operation & Microcycle::Read) {
uint16_t result = 0xffff; uint16_t result = 0xffff;
@ -142,7 +142,11 @@ class ConcreteMachine:
if(cycle.operation & Microcycle::Read) { if(cycle.operation & Microcycle::Read) {
cycle.set_value16(0xffff); cycle.set_value16(0xffff);
} }
LOG("Unmapped " << (cycle.operation & Microcycle::Read ? "read from " : "write to ") << PADHEX(4) << *cycle.address << " of " << cycle.value16());
// Don't log for the region that is definitely just ROM this machine doesn't have.
if(address < 0xf0'0000) {
LOG("Unmapped " << (cycle.operation & Microcycle::Read ? "read from " : "write to ") << PADHEX(4) << *cycle.address << " of " << cycle.value16());
}
} }
} }
} else { } else {

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@ -133,6 +133,14 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
cycle.set_value16(0x8080); cycle.set_value16(0x8080);
break; break;
case Write(0x034):
LOG("TODO: pot port start");
break;
case Read(0x016):
LOG("TODO: pot port read");
cycle.set_value16(0xff00);
break;
// Disk DMA. // Disk DMA.
case Write(0x020): case Write(0x022): case Write(0x024): case Write(0x020): case Write(0x022): case Write(0x024):
case Write(0x026): case Write(0x026):