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Completes addressing modes for ADDI/etc/etc.
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@ -665,6 +665,15 @@ struct ProcessorStorageConstructor {
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op(Action::PerformOperation, seq("nw", { ea(1) }, !is_byte_access));
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break;
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case l(d8AnXn): // [EORI/ORI/ANDI/SUBI/ADDI].l #, (d8, An, Xn)
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case l(d16An): // [EORI/ORI/ANDI/SUBI/ADDI].l #, (d16, An)
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op(Action::None, seq("np"));
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op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
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op( calc_action_for_mode(mode) | MicroOp::DestinationMask,
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seq(pseq("np nRd+ nrd np", mode), { ea(1), ea(1) }));
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op(Action::PerformOperation, seq("nw- nW", { ea(1), ea(1) }));
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break;
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case bw(XXXw): // [EORI/ORI/ANDI/SUBI/ADDI].bw #, (xxx).w
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op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
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op( int(Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask,
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@ -672,12 +681,28 @@ struct ProcessorStorageConstructor {
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op(Action::PerformOperation, seq("nw", { ea(1) }, !is_byte_access));
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break;
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case l(XXXw): // [EORI/ORI/ANDI/SUBI/ADDI].l #, (xxx).w
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op(Action::None, seq("np"));
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op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
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op( int(Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask,
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seq("np nRd+ nrd np", { ea(1), ea(1) }));
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op(Action::PerformOperation, seq("nw- nW", { ea(1), ea(1) }));
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break;
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case bw(XXXl): // [EORI/ORI/ANDI/SUBI/ADDI].bw #, (xxx).l
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op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np np"));
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op( int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask,
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seq("np nrd np", { ea(1) }, !is_byte_access));
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op(Action::PerformOperation, seq("nw", { ea(1) }, !is_byte_access));
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break;
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case l(XXXl): // [EORI/ORI/ANDI/SUBI/ADDI].l #, (xxx).l
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op(Action::None, seq("np"));
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op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask, seq("np np"));
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op( int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask,
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seq("np nRd+ nrd np", { ea(1), ea(1) }));
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op(Action::PerformOperation, seq("nw- nW", { ea(1), ea(1) }));
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break;
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}
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} break;
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