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Consolidates JSR and BSR preparation.

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This commit is contained in:
Thomas Harte 2019-04-16 21:29:37 -04:00
parent 9b7ca6f271
commit d8d974e2d7
3 changed files with 23 additions and 33 deletions
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11
Processors/68000/Implementation/68000Implementation.hpp
View File

@ -1045,15 +1045,10 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
}
} break;
case int(MicroOp::Action::PrepareJSR):
destination_bus_data_[0] = program_counter_;
address_[7].full -= 4;
effective_address_[1].full = address_[7].full;
break;
case int(MicroOp::Action::PrepareBSR):
case int(MicroOp::Action::PrepareJSRBSR):
// If the lowest byte of the instruction is non-zero then there's no 16-bit offset after it, so the
// return address should be two less.
// return address should be two less. This holds for both a BSR and a JSR as a JSR always has bit
// 7 set.
destination_bus_data_[0].full = (decoded_instruction_ & 0xff) ? program_counter_.full - 2 : program_counter_.full;
address_[7].full -= 4;
effective_address_[1].full = address_[7].full;

36
Processors/68000/Implementation/68000Storage.cpp
View File

@ -608,21 +608,21 @@ struct ProcessorStorageConstructor {
switch(is_long_word_access ? l(mode) : bw(mode)) {
default: continue;
case bw(Dn):
case bw(Dn): // [EORI/ORI/ANDI/SUBI/ADDI].bw #, Dn
op( int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask,
seq("np np", { a(ea_register) }, !is_byte_access));
op(Action::PerformOperation);
break;
case l(Dn):
case l(Dn): // [EORI/ORI/ANDI/SUBI/ADDI].l #, Dn
op(Action::None, seq("np"));
op( int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask,
seq("np np nn", { a(ea_register) }, !is_byte_access));
op(Action::PerformOperation);
break;
case bw(Ind):
case bw(PostInc):
case bw(Ind): // [EORI/ORI/ANDI/SUBI/ADDI].bw #, (An)
case bw(PostInc): // [EORI/ORI/ANDI/SUBI/ADDI].bw #, (An)+
op( int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask,
seq("np nrd np", { a(ea_register) }, !is_byte_access));
op(Action::PerformOperation, seq("nw", { a(ea_register) }, !is_byte_access));
@ -631,8 +631,8 @@ struct ProcessorStorageConstructor {
}
break;
case l(Ind):
case l(PostInc):
case l(Ind): // [EORI/ORI/ANDI/SUBI/ADDI].l #, (An)
case l(PostInc): // [EORI/ORI/ANDI/SUBI/ADDI].l #, (An)+
op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask, seq("np"));
op( int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask,
seq("np nRd+ nrd np", { ea(1), ea(1) }));
@ -642,14 +642,14 @@ struct ProcessorStorageConstructor {
}
break;
case bw(PreDec):
case bw(PreDec): // [EORI/ORI/ANDI/SUBI/ADDI].bw #, -(An)
op(int(is_byte_access ? Action::Decrement1 : Action::Decrement2) | MicroOp::DestinationMask);
op( int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask,
seq("np n nrd np", { a(ea_register) }, !is_byte_access));
op(Action::PerformOperation, seq("nw", { a(ea_register) }, !is_byte_access));
break;
case l(PreDec):
case l(PreDec): // [EORI/ORI/ANDI/SUBI/ADDI].l #, -(An)
op(int(Action::Decrement4) | MicroOp::DestinationMask);
op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask, seq("np"));
op( int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask,
@ -657,22 +657,22 @@ struct ProcessorStorageConstructor {
op(Action::PerformOperation, seq("nw- nW", { ea(1), ea(1) }));
break;
case bw(d8AnXn):
case bw(d16An):
case bw(d8AnXn): // [EORI/ORI/ANDI/SUBI/ADDI].bw #, (d8, An, Xn)
case bw(d16An): // [EORI/ORI/ANDI/SUBI/ADDI].bw #, (d16, An)
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
op( calc_action_for_mode(mode) | MicroOp::DestinationMask,
seq(pseq("np nrd np", mode), { ea(1) }, !is_byte_access));
op(Action::PerformOperation, seq("nw", { ea(1) }, !is_byte_access));
break;
case bw(XXXw):
case bw(XXXw): // [EORI/ORI/ANDI/SUBI/ADDI].bw #, (xxx).w
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
op( int(Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask,
seq("np nrd np", { ea(1) }, !is_byte_access));
op(Action::PerformOperation, seq("nw", { ea(1) }, !is_byte_access));
break;
case bw(XXXl):
case bw(XXXl): // [EORI/ORI/ANDI/SUBI/ADDI].bw #, (xxx).l
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np np"));
op( int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask,
seq("np nrd np", { ea(1) }, !is_byte_access));
@ -1045,7 +1045,7 @@ struct ProcessorStorageConstructor {
// This is BSR, which is unconditional and means pushing a return address to the stack first.
// Push the return address to the stack.
op(Action::PrepareBSR, seq("n nW+ nw", { ea(1), ea(1) }));
op(Action::PrepareJSRBSR, seq("n nW+ nw", { ea(1), ea(1) }));
}
// This is Bcc.
@ -1728,33 +1728,33 @@ struct ProcessorStorageConstructor {
default: continue;
case Ind: // JSR (An)
storage_.instructions[instruction].source = &storage_.address_[ea_register];
op(Action::PrepareJSR);
op(Action::PrepareJSRBSR);
op(Action::PerformOperation, seq("np nW+ nw np", { ea(1), ea(1) }));
break;
case d16PC: // JSR (d16, PC)
case d16An: // JSR (d16, An)
op(Action::PrepareJSR);
op(Action::PrepareJSRBSR);
op(calc_action_for_mode(mode) | MicroOp::SourceMask);
op(Action::PerformOperation, seq("n np nW+ nw np", { ea(1), ea(1) }));
break;
case d8PCXn: // JSR (d8, PC, Xn)
case d8AnXn: // JSR (d8, An, Xn)
op(Action::PrepareJSR);
op(Action::PrepareJSRBSR);
op(calc_action_for_mode(mode) | MicroOp::SourceMask);
op(Action::PerformOperation, seq("n nn np nW+ nw np", { ea(1), ea(1) }));
break;
case XXXl: // JSR (xxx).L
op(Action::None, seq("np"));
op(Action::PrepareJSR);
op(Action::PrepareJSRBSR);
op(address_assemble_for_mode(mode) | MicroOp::SourceMask);
op(Action::PerformOperation, seq("n np nW+ nw np", { ea(1), ea(1) }));
break;
case XXXw: // JSR (xxx).W
op(Action::PrepareJSR);
op(Action::PrepareJSRBSR);
op(address_assemble_for_mode(mode) | MicroOp::SourceMask);
op(Action::PerformOperation, seq("n np nW+ nw np", { ea(1), ea(1) }));
break;

9
Processors/68000/Implementation/68000Storage.hpp
View File

@ -228,15 +228,10 @@ class ProcessorStorage {
/// Performs write-back of pre-decrement address.
MOVEMtoMComplete,
// (i) copies the current program counter to destination_bus_data_;
// (i) inspects the prefetch queue to determine the length of this instruction and copies the next PC to destination_bus_data_;
// (ii) copies the stack pointer minus 4 to effective_address_[1];
// (iii) decrements the stack pointer by four.
PrepareJSR,
// (i) inspects the prefetch queue to determine the length of this BSR and copies the next PC to destination_bus_data_;
// (ii) copies the stack pointer minus 4 to effective_address_[1];
// (iii) decrements the stack pointer by four.
PrepareBSR,
PrepareJSRBSR,
// (i) copies the stack pointer to effective_address_[0];
// (ii) increments the stack pointer by four.