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Corrected CP[I/D]R termination logic; all tests now passing to the extent of interrogation.
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@ -159,7 +159,6 @@ class FUSETests: XCTestCase {
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XCTAssert(inputArray != nil && outputArray != nil)
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XCTAssert(inputArray != nil && outputArray != nil)
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var index = 0
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var index = 0
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// var failures = 0
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for item in inputArray {
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for item in inputArray {
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let itemDictionary = item as! [String: Any]
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let itemDictionary = item as! [String: Any]
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let outputDictionary = outputArray[index] as! [String: Any]
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let outputDictionary = outputArray[index] as! [String: Any]
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@ -167,10 +166,6 @@ class FUSETests: XCTestCase {
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let name = itemDictionary["name"] as! String
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let name = itemDictionary["name"] as! String
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// if name != "eda3" {
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// continue;
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// }
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let initialState = RegisterState(dictionary: itemDictionary["state"] as! [String: Any])
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let initialState = RegisterState(dictionary: itemDictionary["state"] as! [String: Any])
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let targetState = RegisterState(dictionary: outputDictionary["state"] as! [String: Any])
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let targetState = RegisterState(dictionary: outputDictionary["state"] as! [String: Any])
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@ -195,15 +190,8 @@ class FUSETests: XCTestCase {
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let finalState = RegisterState(machine: machine)
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let finalState = RegisterState(machine: machine)
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XCTAssertEqual(finalState, targetState, "Failed \(name)")
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XCTAssertEqual(finalState, targetState, "Failed \(name)")
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// if finalState != targetState {
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// failures = failures + 1
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// if failures == 5 {
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// return
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// }
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// }
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// TODO compare bus operations and final memory state
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// TODO compare bus operations and final memory state
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}
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}
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}
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}
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}
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}
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@ -1122,7 +1122,7 @@ template <class T> class Processor: public MicroOpScheduler<MicroOp> {
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case MicroOp::CPDR:
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case MicroOp::CPDR:
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case MicroOp::CPIR: {
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case MicroOp::CPIR: {
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CPxR_STEP(MicroOp::CPIR);
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CPxR_STEP(MicroOp::CPIR);
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REPEAT(bc_.full);
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REPEAT(bc_.full && sign_result_);
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} break;
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} break;
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case MicroOp::CPD:
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case MicroOp::CPD:
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