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Fix interrupting sync.
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@@ -161,7 +161,7 @@ public:
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bus state and determines what output to produce based on the current palette and mode.
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*/
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void perform_bus_cycle(const Motorola::CRTC::BusState &state) {
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system_via_.set_control_line_input<MOS::MOS6522::Port::A, MOS::MOS6522::Line::One>(state.hsync);
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system_via_.set_control_line_input<MOS::MOS6522::Port::A, MOS::MOS6522::Line::One>(state.vsync);
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// // The gate array waits 2us to react to the CRTC's vsync signal, and then
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// // caps output at 4us. Since the clock rate is 1Mhz, that's 2 and 4 cycles,
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