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mirror of https://github.com/TomHarte/CLK.git synced 2026-04-19 19:16:34 +00:00

Fix interrupting sync.

This commit is contained in:
Thomas Harte
2025-09-15 23:28:38 -04:00
parent 493bf0a666
commit c350f6fe5e
+1 -1
View File
@@ -161,7 +161,7 @@ public:
bus state and determines what output to produce based on the current palette and mode.
*/
void perform_bus_cycle(const Motorola::CRTC::BusState &state) {
system_via_.set_control_line_input<MOS::MOS6522::Port::A, MOS::MOS6522::Line::One>(state.hsync);
system_via_.set_control_line_input<MOS::MOS6522::Port::A, MOS::MOS6522::Line::One>(state.vsync);
// // The gate array waits 2us to react to the CRTC's vsync signal, and then
// // caps output at 4us. Since the clock rate is 1Mhz, that's 2 and 4 cycles,