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Ensures that page-crossing indexing no longer causes an extra read of an invalid address on the 65C02.
It rereads the last byte of the instruction stream instead.
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@ -436,32 +436,42 @@ if(number_of_cycles <= Cycles(0)) break;
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// MARK: - Addressing Mode Work
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#define page_crossing_stall_read() \
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if(is_65c02(personality)) { \
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throwaway_read(pc_.full - 1); \
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} else { \
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throwaway_read(address_.full); \
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}
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case CycleAddXToAddressLow:
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nextAddress.full = address_.full + x_;
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address_.bytes.low = nextAddress.bytes.low;
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if(address_.bytes.high != nextAddress.bytes.high) {
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throwaway_read(address_.full);
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page_crossing_stall_read();
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break;
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}
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continue;
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case CycleAddXToAddressLowRead:
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nextAddress.full = address_.full + x_;
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address_.bytes.low = nextAddress.bytes.low;
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throwaway_read(address_.full);
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page_crossing_stall_read();
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break;
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case CycleAddYToAddressLow:
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nextAddress.full = address_.full + y_;
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address_.bytes.low = nextAddress.bytes.low;
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if(address_.bytes.high != nextAddress.bytes.high) {
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throwaway_read(address_.full);
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page_crossing_stall_read();
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break;
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}
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continue;
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case CycleAddYToAddressLowRead:
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nextAddress.full = address_.full + y_;
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address_.bytes.low = nextAddress.bytes.low;
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throwaway_read(address_.full);
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page_crossing_stall_read();
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break;
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#undef page_crossing_stall_read
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case OperationCorrectAddressHigh:
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address_.full = nextAddress.full;
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continue;
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@ -17,10 +17,12 @@ class ProcessorStorage {
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protected:
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ProcessorStorage(Personality);
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/*
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/*!
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This emulation functions by decomposing instructions into micro programs, consisting of the micro operations
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as per the enum below. Each micro op takes at most one cycle. By convention, those called CycleX take a cycle
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defined by MicroOp. Each micro op takes at most one cycle. By convention, those called CycleX take a cycle
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to perform whereas those called OperationX occur for free (so, in effect, their cost is loaded onto the next cycle).
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This micro-instruction set was put together in a fairly ad hoc fashion, I'm afraid, so is unlikely to be optimal.
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*/
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enum MicroOp {
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CycleFetchOperation, // fetches (PC) to operation_, storing PC to last_operation_pc_ before incrementing it
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@ -72,10 +74,10 @@ class ProcessorStorage {
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CycleLoadAddessZeroX, // copies (operand_+x)&0xff to address_, increments the PC, and reads from operand_, throwing away the result
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CycleLoadAddessZeroY, // copies (operand_+y)&0xff to address_, increments the PC, and reads from operand_, throwing away the result
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CycleAddXToAddressLow, // calculates address_ + x and stores it to next_address_; copies next_address_.l back to address_.l; if address_ now does not equal next_address_, schedules a throwaway read from address_
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CycleAddYToAddressLow, // calculates address_ + y and stores it to next_address_; copies next_address_.l back to address_.l; if address_ now does not equal next_address_, schedules a throwaway read from address_
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CycleAddXToAddressLowRead, // calculates address_ + x and stores it to next_address; copies next_address.l back to address_.l; schedules a throwaway read from address_
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CycleAddYToAddressLowRead, // calculates address_ + y and stores it to next_address; copies next_address.l back to address_.l; schedules a throwaway read from address_
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CycleAddXToAddressLow, // calculates address_ + x and stores it to next_address_; copies next_address_.l back to address_.l; 6502: if address_ now does not equal next_address_, schedules a throwaway read from address_; 65C02: schedules a throaway read from PC-1
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CycleAddYToAddressLow, // calculates address_ + y and stores it to next_address_; copies next_address_.l back to address_.l; 6502: if address_ now does not equal next_address_, schedules a throwaway read from address_; 65C02: schedules a throaway read from PC-1
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CycleAddXToAddressLowRead, // calculates address_ + x and stores it to next_address; copies next_address.l back to address_.l; 6502: schedules a throwaway read from address_; 65C02: schedules a throaway read from PC-1
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CycleAddYToAddressLowRead, // calculates address_ + y and stores it to next_address; copies next_address.l back to address_.l; 6502: schedules a throwaway read from address_; 65C02: schedules a throaway read from PC-1
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OperationCorrectAddressHigh, // copies next_address_ to address_
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OperationIncrementPC, // increments the PC
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