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https://github.com/TomHarte/CLK.git
synced 2026-04-21 17:16:44 +00:00
Incorporate IRQ timing test; accept that it must be tested within the access macro.
This commit is contained in:
Thomas Harte
@@ -35,6 +35,11 @@ struct BusHandler {
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};
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std::vector<Access> accesses;
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void clear() {
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opcode_reads = 0;
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accesses.clear();
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}
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template <CPU::MOS6502Mk2::BusOperation operation, typename AddressT>
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Cycles perform(const AddressT address, CPU::MOS6502Mk2::data_t<operation> data) {
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// Check for end of tests.
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@@ -73,7 +78,7 @@ CPU::MOS6502Mk2::Registers registersFrom(NSDictionary *dictionary) {
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}
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template <CPU::MOS6502Mk2::Model model>
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void testExecution(NSDictionary *test, BusHandler &handler) {
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CPU::MOS6502Mk2::Processor<model, Traits> make_processor(NSDictionary *test, BusHandler &handler) {
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CPU::MOS6502Mk2::Processor<model, Traits> processor(handler);
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NSDictionary *initial = test[@"initial"];
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@@ -84,33 +89,24 @@ void testExecution(NSDictionary *test, BusHandler &handler) {
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}
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processor.template set<CPU::MOS6502Mk2::Line::PowerOn>(false);
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handler.opcode_reads = 0;
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handler.accesses.clear();
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handler.clear();
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return processor;
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}
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const uint8_t opcode = handler.memory[initial_registers.pc.full];
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template <CPU::MOS6502Mk2::Model model>
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void testExecution(NSDictionary *test, BusHandler &handler) {
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auto processor = make_processor<model>(test, handler);
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try {
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processor.run_for(Cycles(11)); // To catch the entirety of a JAM as in the JSON.
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} catch (TestComplete) {}
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NSDictionary *final = test[@"final"];
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const auto final_registers = registersFrom(final);
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XCTAssertEqual(final_registers.a, processor.registers().a);
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XCTAssertEqual(final_registers.x, processor.registers().x);
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XCTAssertEqual(final_registers.y, processor.registers().y);
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XCTAssertEqual(final_registers.s, processor.registers().s);
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XCTAssert(final_registers.pc == processor.registers().pc);
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XCTAssert(final_registers.flags <=> processor.registers().flags == std::strong_ordering::equal);
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const uint8_t opcode = handler.memory[processor.registers().pc.full];
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std::bitset<16> ignore_addresses;
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const auto instruction = CPU::MOS6502Mk2::Decoder<model>::decode(opcode);
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// 65c02 exceptions:
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//
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// * I suspect the NOPs are mistimed;
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// * I am confident that the extra accessed address following an immediate decimal arithmetic is incorrect; and
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// * I am certain that the extra address in JMP (abs,X) is wrong, being a regression.
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std::bitset<16> ignore_addresses;
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if(is_65c02(model)) {
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const auto instruction = CPU::MOS6502Mk2::Decoder<model>::decode(opcode);
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if(
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instruction.operation == CPU::MOS6502Mk2::Operation::NOP ||
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instruction.operation == CPU::MOS6502Mk2::Operation::FastNOP
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@@ -124,10 +120,23 @@ void testExecution(NSDictionary *test, BusHandler &handler) {
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instruction.operation == CPU::MOS6502Mk2::Operation::SBC
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) &&
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instruction.mode == CPU::MOS6502Mk2::AddressingMode::Immediate &&
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initial_registers.flags.decimal;
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processor.registers().flags.decimal;
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ignore_addresses[3] = instruction.mode == CPU::MOS6502Mk2::AddressingMode::JMPAbsoluteIndexedIndirect;
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}
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try {
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processor.run_for(Cycles(11)); // To catch the entirety of a JAM as in the JSON.
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} catch (TestComplete) {}
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NSDictionary *final = test[@"final"];
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const auto final_registers = registersFrom(final);
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XCTAssertEqual(final_registers.a, processor.registers().a);
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XCTAssertEqual(final_registers.x, processor.registers().x);
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XCTAssertEqual(final_registers.y, processor.registers().y);
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XCTAssertEqual(final_registers.s, processor.registers().s);
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XCTAssert(final_registers.pc == processor.registers().pc);
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XCTAssert(final_registers.flags <=> processor.registers().flags == std::strong_ordering::equal);
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auto found_cycle = handler.accesses.begin();
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for(NSArray *cycle in test[@"cycles"]) {
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XCTAssertNotEqual(found_cycle, handler.accesses.end());
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@@ -144,6 +153,34 @@ void testExecution(NSDictionary *test, BusHandler &handler) {
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++found_cycle;
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}
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XCTAssertEqual(found_cycle, handler.accesses.end());
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// JAM won't segue into an interrupt; for RTI I'd need better to test unstacked flags.
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if(
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instruction.operation == CPU::MOS6502Mk2::Operation::JAM ||
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instruction.operation == CPU::MOS6502Mk2::Operation::RTI
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) {
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return;
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}
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// Now try again, setting IRQ one before the previous end and not before,
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// and resetting it straight afterwards. Make sure that causes an interrupt to be taken.
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const auto last_length = handler.accesses.size();
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{
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auto repeat_processor = make_processor<model>(test, handler);
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const bool should_interrupt =
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instruction.operation != CPU::MOS6502Mk2::Operation::BRK &&
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repeat_processor.registers().flags.inverse_interrupt;
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try {
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repeat_processor.run_for(Cycles(last_length - 1));
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repeat_processor.template set<CPU::MOS6502Mk2::Line::IRQ>(true);
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repeat_processor.run_for(Cycles(1));
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repeat_processor.template set<CPU::MOS6502Mk2::Line::IRQ>(false);
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repeat_processor.run_for(Cycles(10));
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} catch (TestComplete) {}
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XCTAssertEqual(handler.accesses.size(), last_length + (should_interrupt ? 7 : 0));
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}
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}
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void testExecution(CPU::MOS6502Mk2::Model model, NSDictionary *test, BusHandler &handler) {
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@@ -22,10 +22,15 @@ namespace CPU::MOS6502Mk2 {
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template <Model model, typename Traits>
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void Processor<model, Traits>::restart_operation_fetch() {
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Storage::resume_point_ = Storage::ResumePoint::FetchDecode;
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Storage::cycles_ = Cycles(0);
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}
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template <Model model, typename Traits>
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void Processor<model, Traits>::run_for(const Cycles cycles) {
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using ResumePoint = Storage::ResumePoint;
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using InterruptRequest = Storage::Inputs::InterruptRequest;
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auto ®isters = Storage::registers_;
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Storage::cycles_ += cycles;
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if(Storage::cycles_ <= Cycles(0)) return;
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@@ -35,6 +40,11 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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}
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static void assign(const uint8_t &, const Data::Writeable) {}
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};
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const auto check_interrupt = [&] {
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Storage::captured_interrupt_requests_ =
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Storage::inputs_.interrupt_requests &
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(Storage::registers_.flags.inverse_interrupt | ~InterruptRequest::IRQ);
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};
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#define restore_point() (__COUNTER__ + int(ResumePoint::Max) + int(AddressingMode::Max))
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@@ -47,6 +57,7 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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static constexpr int location = restore_point(); \
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[[fallthrough]]; case location: \
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[[maybe_unused]] access_label(): \
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check_interrupt(); \
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\
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if constexpr (Traits::pause_precision >= PausePrecision::AnyCycle) { \
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if(Storage::cycles_ <= Cycles(0)) { \
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@@ -78,19 +89,11 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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#define access_program(name) int(ResumePoint::Max) + int(AddressingMode::name)
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using ResumePoint = Storage::ResumePoint;
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using InterruptRequest = Storage::Inputs::InterruptRequest;
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auto ®isters = Storage::registers_;
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Data::Writeable throwaway;
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const auto index = [&] {
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return Storage::decoded_.index == Index::X ? registers.x : registers.y;
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};
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const auto check_interrupt = [&] {
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Storage::captured_interrupt_requests_ =
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Storage::inputs_.interrupt_requests & (Storage::registers_.flags.
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inverse_interrupt | ~InterruptRequest::IRQ);
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};
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const auto perform_operation = [&] {
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CPU::MOS6502Mk2::perform<model>(
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Storage::decoded_.operation,
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@@ -137,7 +140,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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}
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// Read.
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check_interrupt();
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access(BusOperation::Read, ZeroPage(Storage::address_.halves.low), Storage::operand_);
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if(Storage::decoded_.type == Type::Read) {
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perform_operation();
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@@ -153,7 +155,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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// Write.
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access_zero_write:
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check_interrupt();
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perform_operation();
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access(BusOperation::Write, ZeroPage(Storage::address_.halves.low), Storage::operand_);
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@@ -161,7 +162,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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access_zero_65c02_decimal:
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access(BusOperation::Read, ZeroPage(Storage::address_.halves.low), Storage::operand_);
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check_interrupt();
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access(BusOperation::Read, ZeroPage(Storage::address_.halves.low), Storage::operand_);
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perform_operation();
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goto fetch_decode;
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@@ -185,7 +185,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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}
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// Read.
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check_interrupt();
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access(BusOperation::Read, Literal(Storage::address_.full), Storage::operand_);
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if(Storage::decoded_.type == Type::Read) {
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perform_operation();
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@@ -201,7 +200,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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// Write.
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access_absolute_write:
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check_interrupt();
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perform_operation();
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access(BusOperation::Write, Literal(Storage::address_.full), Storage::operand_);
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@@ -209,7 +207,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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access_absolute_65c02_decimal:
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access(BusOperation::Read, Literal(Storage::address_.full), Storage::operand_);
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check_interrupt();
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perform_operation();
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access(BusOperation::Read, Literal(Storage::address_.full), Storage::operand_);
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goto fetch_decode;
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@@ -243,7 +240,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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}
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}
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check_interrupt();
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access(BusOperation::Read, Literal(registers.pc.full), Storage::operand_);
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Storage::resume_point_ = ResumePoint::Max + int(Storage::decoded_.mode);
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@@ -263,7 +259,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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goto fetch_decode;
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immediate_65c02_decimal:
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check_interrupt();
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access(BusOperation::Read, Literal(registers.pc.full), Storage::operand_);
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++registers.pc.full;
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@@ -283,13 +278,11 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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case access_program(Pull):
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access(BusOperation::Read, Stack(registers.s), Storage::operand_);
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check_interrupt();
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access(BusOperation::Read, Stack(registers.inc_s()), Storage::operand_);
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perform_operation();
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goto fetch_decode;
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case access_program(Push):
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check_interrupt();
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perform_operation();
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access(BusOperation::Write, Stack(registers.dec_s()), Storage::operand_);
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goto fetch_decode;
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@@ -350,9 +343,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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// MARK: - Zero indexed.
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case access_program(ZeroIndexed):
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if constexpr (is_65c02(model)) {
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check_interrupt();
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}
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Storage::address_.halves.low = Storage::operand_;
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access(BusOperation::Read, ZeroPage(Storage::operand_), throwaway);
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Storage::address_.halves.low += index();
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@@ -363,7 +353,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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case access_program(ZeroIndirect):
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access(BusOperation::Read, ZeroPage(Storage::operand_++), Storage::address_.halves.low);
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check_interrupt();
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access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::address_.halves.high);
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goto access_absolute;
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@@ -372,10 +361,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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case access_program(Absolute):
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++registers.pc.full;
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if constexpr (is_65c02(model)) {
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check_interrupt();
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}
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Storage::address_.halves.low = Storage::operand_;
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access(BusOperation::Read, Literal(registers.pc.full), Storage::address_.halves.high);
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@@ -387,9 +372,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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++registers.pc.full;
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// Read top half of address.
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if constexpr (is_65c02(model)) {
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check_interrupt();
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}
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Storage::address_.halves.low = Storage::operand_;
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access(BusOperation::Read, Literal(registers.pc.full), Storage::address_.halves.high);
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@@ -409,7 +391,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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goto access_absolute;
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absolute_indexed_65c02_tail:
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check_interrupt();
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access(BusOperation::Read, Literal(registers.pc.full), throwaway);
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goto access_absolute;
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@@ -420,7 +401,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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// Read top half of address.
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Storage::address_.halves.low = Storage::operand_;
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check_interrupt();
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access(BusOperation::Read, Literal(registers.pc.full), Storage::address_.halves.high);
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// If this is a read and the top byte doesn't need adjusting, skip that cycle.
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@@ -430,7 +410,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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goto access_absolute;
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}
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check_interrupt();
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access(BusOperation::Read, Literal(registers.pc.full), throwaway);
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goto access_absolute;
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@@ -441,9 +420,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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Storage::operand_ += registers.x;
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access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::address_.halves.low);
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++Storage::operand_;
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if constexpr (is_65c02(model)) {
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check_interrupt();
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}
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access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::address_.halves.high);
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goto access_absolute;
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@@ -453,9 +429,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::address_.halves.low);
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++Storage::operand_;
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if constexpr (is_65c02(model)) {
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check_interrupt();
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}
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access(BusOperation::Read, ZeroPage(Storage::operand_), Storage::address_.halves.high);
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Storage::operand_ = Storage::address_.halves.high;
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@@ -475,7 +448,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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goto access_absolute;
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indirect_indexed_65c02_tail:
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check_interrupt();
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access(BusOperation::Read, Literal(registers.pc.full), throwaway);
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goto access_absolute;
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@@ -512,7 +484,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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break;
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}
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check_interrupt();
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access(BusOperation::Write, Literal(Storage::address_.full), Storage::operand_);
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goto fetch_decode;
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@@ -533,7 +504,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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access(BusOperation::Read, Literal(Storage::address_.full), throwaway);
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std::swap(Storage::address_.halves.high, Storage::operand_);
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check_interrupt();
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assert(Storage::decoded_.operation == Operation::SHA);
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Operations::sha(registers, Storage::address_, Storage::operand_, Storage::did_adjust_top_);
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access(BusOperation::Write, Literal(Storage::address_.full), Storage::operand_);
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@@ -566,8 +536,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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access(BusOperation::Read, Stack(registers.s), throwaway);
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access(BusOperation::Write, Stack(registers.dec_s()), registers.pc.halves.high);
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access(BusOperation::Write, Stack(registers.dec_s()), registers.pc.halves.low);
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check_interrupt();
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access(BusOperation::Read, Literal(registers.pc.full), registers.pc.halves.high);
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registers.pc.halves.low = Storage::operand_;
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@@ -580,7 +548,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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registers.flags = Flags(Storage::operand_);
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access(BusOperation::Read, Stack(registers.inc_s()), registers.pc.halves.low);
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check_interrupt();
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access(BusOperation::Read, Stack(registers.inc_s()), registers.pc.halves.high);
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goto fetch_decode;
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@@ -590,8 +557,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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access(BusOperation::Read, Stack(registers.inc_s()), registers.pc.halves.low);
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access(BusOperation::Read, Stack(registers.inc_s()), registers.pc.halves.high);
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check_interrupt();
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access(BusOperation::Read, Literal(registers.pc.full), throwaway);
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++registers.pc.full;
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@@ -599,7 +564,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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case access_program(JMPAbsolute):
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++registers.pc.full;
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check_interrupt();
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access(BusOperation::Read, Literal(registers.pc.full), registers.pc.halves.high);
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registers.pc.halves.low = Storage::operand_;
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@@ -612,7 +576,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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access(BusOperation::Read, Literal(Storage::address_.full), registers.pc.halves.low);
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++Storage::address_.halves.low;
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check_interrupt();
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access(BusOperation::Read, Literal(Storage::address_.full), registers.pc.halves.high);
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if constexpr (!is_65c02(model)) {
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@@ -620,7 +583,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
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}
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||||
Storage::address_.halves.high += !Storage::address_.halves.low;
|
||||
check_interrupt();
|
||||
access(BusOperation::Read, Literal(Storage::address_.full), registers.pc.halves.high);
|
||||
|
||||
goto fetch_decode;
|
||||
@@ -656,7 +618,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
|
||||
}
|
||||
|
||||
access(BusOperation::Read, Vector(0xfe), registers.pc.halves.low);
|
||||
check_interrupt();
|
||||
access(BusOperation::Read, Vector(0xff), registers.pc.halves.high);
|
||||
goto fetch_decode;
|
||||
|
||||
@@ -668,7 +629,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
|
||||
Storage::inputs_.interrupt_requests &= ~InterruptRequest::PowerOn;
|
||||
goto reset;
|
||||
}
|
||||
assert(Storage::captured_interrupt_requests_ & (InterruptRequest::IRQ | InterruptRequest::NMI));
|
||||
|
||||
access(BusOperation::Write, Stack(registers.dec_s()), registers.pc.halves.high);
|
||||
access(BusOperation::Write, Stack(registers.dec_s()), registers.pc.halves.low);
|
||||
@@ -687,13 +647,11 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
|
||||
}
|
||||
|
||||
access(BusOperation::Read, Vector(0xfe), registers.pc.halves.low);
|
||||
check_interrupt();
|
||||
access(BusOperation::Read, Vector(0xff), registers.pc.halves.high);
|
||||
goto fetch_decode;
|
||||
|
||||
nmi:
|
||||
access(BusOperation::Read, Vector(0xfa), registers.pc.halves.low);
|
||||
check_interrupt();
|
||||
access(BusOperation::Read, Vector(0xfb), registers.pc.halves.high);
|
||||
goto fetch_decode;
|
||||
|
||||
@@ -706,7 +664,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
|
||||
if constexpr (is_65c02(model)) registers.flags.decimal = 0;
|
||||
|
||||
access(BusOperation::Read, Vector(0xfc), registers.pc.halves.low);
|
||||
check_interrupt();
|
||||
access(BusOperation::Read, Vector(0xfd), registers.pc.halves.high);
|
||||
goto fetch_decode;
|
||||
|
||||
@@ -717,7 +674,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
|
||||
Storage::resume_point_ = access_program(STP);
|
||||
return;
|
||||
}
|
||||
check_interrupt();
|
||||
access(BusOperation::None, Vector(0xff), Data::NoValue{});
|
||||
if(Storage::captured_interrupt_requests_ & (InterruptRequest::Reset | InterruptRequest::PowerOn)) {
|
||||
goto fetch_decode;
|
||||
@@ -730,7 +686,6 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
|
||||
Storage::resume_point_ = access_program(WAI);
|
||||
return;
|
||||
}
|
||||
check_interrupt();
|
||||
access(BusOperation::Ready, Vector(0xff), Data::NoValue{});
|
||||
if(Storage::captured_interrupt_requests_) {
|
||||
goto fetch_decode;
|
||||
|
||||
Reference in New Issue
Block a user