mirror of
https://github.com/TomHarte/CLK.git
synced 2025-04-06 10:38:16 +00:00
Introduces a first test of PowerPC decoding.
Corrected as a result: the bcx conditional, that stdu is 64-bit only, extraction of the li field.
This commit is contained in:
Thomas Harte
parent
1a3effc692
commit
c934e22cee
@ -185,6 +185,7 @@
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@ -3479,6 +3481,7 @@
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4BC0CB272446BC7B00A79DBB /* OPLTests.mm */,
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4B121F9A1E06293F00BFDA12 /* PCMSegmentEventSourceTests.mm */,
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4BD4A8CF1E077FD20020D856 /* PCMTrackTests.mm */,
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4B3F76B825A1635300178AEC /* PowerPCDecoderTests.mm */,
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4BE76CF822641ED300ACD6FA /* QLTests.mm */,
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4B2AF8681E513FC20027EE29 /* TIATests.mm */,
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4B1D08051E0F7A1100763741 /* TimeTests.mm */,
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@ -4919,6 +4922,7 @@
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4B778F4223A5F1A70000D260 /* MemoryFuzzer.cpp in Sources */,
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4B778F0123A5EBA00000D260 /* MacintoshIMG.cpp in Sources */,
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4BFF1D3D2235C3C100838EA1 /* EmuTOSTests.mm in Sources */,
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4B3F76B925A1635300178AEC /* PowerPCDecoderTests.mm in Sources */,
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4B778F0A23A5EC150000D260 /* TapePRG.cpp in Sources */,
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4B778F0823A5EC150000D260 /* CSW.cpp in Sources */,
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4B778F5323A5F23F0000D260 /* SerialBus.cpp in Sources */,
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203
OSBindings/Mac/Clock SignalTests/PowerPCDecoderTests.mm
Normal file
203
OSBindings/Mac/Clock SignalTests/PowerPCDecoderTests.mm
Normal file
@ -0,0 +1,203 @@
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//
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// PowerPCDecoderTests.m
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// Clock Signal
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//
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// Created by Thomas Harte on 02/01/2021.
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// Copyright 2021 Thomas Harte. All rights reserved.
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//
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#import <XCTest/XCTest.h>
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#include "../../../Processors/Decoders/PowerPC/PowerPC.hpp"
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namespace {
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using Operation = CPU::Decoder::PowerPC::Operation;
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}
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@interface PowerPCDecoderTests : XCTestCase
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@end
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/*!
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Tests PowerPC decoding by throwing a bunch of randomly-generated
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word streams and checking that the result matches what I got from a
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disassembler elsewhere.
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*/
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@implementation PowerPCDecoderTests {
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CPU::Decoder::PowerPC::Instruction instructions[32];
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}
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- (void)decode:(const uint32_t *)stream {
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CPU::Decoder::PowerPC::Decoder decoder(CPU::Decoder::PowerPC::Model::MPC601);
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for(int c = 0; c < 32; c++) {
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instructions[c] = decoder.decode(stream[c]);
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}
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}
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- (void)testStream1 {
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const uint32_t stream[] = {
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0x32eeefa5, 0xc2ee0786, 0x80ce552c, 0x88d5f02a,
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0xf8c2e801, 0xe83d5cdf, 0x7fa51fbb, 0xaacea8b0,
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0x7d4d4d21, 0x1314cf89, 0x47e0014b, 0xdf67566d,
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0xfb29a33e, 0x312cbf53, 0x706f1a15, 0xa87b7011,
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0x2107090c, 0xce04935e, 0x642e464a, 0x931e8eba,
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0xee396d5b, 0x4901183d, 0x31ccaa9a, 0x42b61a86,
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0x1ed4751d, 0x86af76e4, 0x151405a9, 0xca0ac015,
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0x60dd1f9d, 0xecff44f6, 0xf2c1110e, 0x9aa6653b,
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};
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[self decode:stream];
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// addic r23,r14,-4187
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XCTAssertEqual(instructions[0].operation, Operation::addic);
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XCTAssertEqual(instructions[0].rD(), 23);
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XCTAssertEqual(instructions[0].rA(), 14);
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XCTAssertEqual(instructions[0].simm(), -4187);
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// lfs f23,1926(r14)
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XCTAssertEqual(instructions[1].operation, Operation::lfs);
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XCTAssertEqual(instructions[1].frD(), 23);
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XCTAssertEqual(instructions[1].rA(), 14);
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XCTAssertEqual(instructions[1].d(), 1926);
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// lwz r6,21804(r14)
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XCTAssertEqual(instructions[2].operation, Operation::lwz);
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XCTAssertEqual(instructions[2].rD(), 6);
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XCTAssertEqual(instructions[2].rA(), 14);
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XCTAssertEqual(instructions[2].d(), 21804);
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// lbz r6,-4054(r21)
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XCTAssertEqual(instructions[3].operation, Operation::lbz);
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XCTAssertEqual(instructions[3].rD(), 6);
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XCTAssertEqual(instructions[3].rA(), 21);
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XCTAssertEqual(instructions[3].d(), -4054);
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// .long 0xf8c2e801
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// .long 0xe83d5cdf
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// .long 0x7fa51fbb
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XCTAssertEqual(instructions[4].operation, Operation::Undefined);
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XCTAssertEqual(instructions[5].operation, Operation::Undefined);
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XCTAssertEqual(instructions[6].operation, Operation::Undefined);
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// lha r22,-22352(r14)
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XCTAssertEqual(instructions[7].operation, Operation::lha);
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XCTAssertEqual(instructions[7].rD(), 22);
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XCTAssertEqual(instructions[7].rA(), 14);
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XCTAssertEqual(instructions[7].d(), -22352);
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// .long 0x7d4d4d21
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// .long 0x1314cf89
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// .long 0x47e0014b
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XCTAssertEqual(instructions[8].operation, Operation::Undefined);
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XCTAssertEqual(instructions[9].operation, Operation::Undefined);
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// CLK decodes this as sc because it ignores reserved bits; the disassembler
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// I used checks the reserved bits. For now: don't test.
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// XCTAssertEqual(instructions[10].operation, Operation::Undefined);
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// stfdu f27,22125(r7)
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XCTAssertEqual(instructions[11].operation, Operation::stfdu);
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XCTAssertEqual(instructions[11].frS(), 27);
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XCTAssertEqual(instructions[11].rA(), 7);
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XCTAssertEqual(instructions[11].d(), 22125);
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// .long 0xfb29a33e
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XCTAssertEqual(instructions[12].operation, Operation::Undefined);
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// addic r9,r12,-16557
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XCTAssertEqual(instructions[13].operation, Operation::addic);
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XCTAssertEqual(instructions[13].rD(), 9);
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XCTAssertEqual(instructions[13].rA(), 12);
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XCTAssertEqual(instructions[13].simm(), -16557);
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// andi. r15,r3,6677
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XCTAssertEqual(instructions[14].operation, Operation::andi_);
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XCTAssertEqual(instructions[14].rA(), 15);
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XCTAssertEqual(instructions[14].rS(), 3);
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XCTAssertEqual(instructions[14].uimm(), 6677);
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// lha r3,28689(r27)
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XCTAssertEqual(instructions[15].operation, Operation::lha);
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XCTAssertEqual(instructions[15].rD(), 3);
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XCTAssertEqual(instructions[15].rA(), 27);
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XCTAssertEqual(instructions[15].d(), 28689);
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// subfic r8,r7,2316
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XCTAssertEqual(instructions[16].operation, Operation::subfic);
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XCTAssertEqual(instructions[16].rD(), 8);
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XCTAssertEqual(instructions[16].rA(), 7);
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XCTAssertEqual(instructions[16].simm(), 2316);
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// lfdu f16,-27810(r4)
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XCTAssertEqual(instructions[17].operation, Operation::lfdu);
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XCTAssertEqual(instructions[17].frD(), 16);
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XCTAssertEqual(instructions[17].rA(), 4);
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XCTAssertEqual(instructions[17].d(), -27810);
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// oris r14,r1,17994
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XCTAssertEqual(instructions[18].operation, Operation::oris);
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XCTAssertEqual(instructions[18].rA(), 14);
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XCTAssertEqual(instructions[18].rS(), 1);
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XCTAssertEqual(instructions[18].uimm(), 17994);
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// stw r24,-28998(r30)
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XCTAssertEqual(instructions[19].operation, Operation::stw);
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XCTAssertEqual(instructions[19].rS(), 24);
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XCTAssertEqual(instructions[19].rA(), 30);
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XCTAssertEqual(instructions[19].d(), -28998);
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// .long 0xee396d5b
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XCTAssertEqual(instructions[20].operation, Operation::Undefined);
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// bl 0x01011890 [disassmebled at address 0x54]
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XCTAssertEqual(instructions[21].operation, Operation::bx);
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XCTAssertEqual(instructions[21].li() + 0x54, 0x01011890);
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XCTAssertTrue(instructions[21].lk());
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XCTAssertFalse(instructions[21].aa());
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// addic r14,r12,-21862
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XCTAssertEqual(instructions[22].operation, Operation::addic);
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XCTAssertEqual(instructions[22].rD(), 14);
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XCTAssertEqual(instructions[22].rA(), 12);
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XCTAssertEqual(instructions[22].simm(), -21862);
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// .long 0x42b61a86 [10101]
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XCTAssertEqual(instructions[23].operation, Operation::Undefined);
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// mulli r22,r20,29981
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XCTAssertEqual(instructions[24].operation, Operation::mulli);
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XCTAssertEqual(instructions[24].rD(), 22);
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XCTAssertEqual(instructions[24].rA(), 20);
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XCTAssertEqual(instructions[24].simm(), 29981);
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// lwzu r21,30436(r15)
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XCTAssertEqual(instructions[25].operation, Operation::lwzu);
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XCTAssertEqual(instructions[25].rD(), 21);
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XCTAssertEqual(instructions[25].rA(), 15);
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XCTAssertEqual(instructions[25].d(), 30436);
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// .long 0x151405a9
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XCTAssertEqual(instructions[26].operation, Operation::Undefined);
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// lfd f16,-16363(r10)
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XCTAssertEqual(instructions[27].operation, Operation::lfd);
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XCTAssertEqual(instructions[27].frD(), 16);
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XCTAssertEqual(instructions[27].rA(), 10);
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XCTAssertEqual(instructions[27].d(), -16363);
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// ori r29,r6,8093
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XCTAssertEqual(instructions[28].operation, Operation::ori);
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XCTAssertEqual(instructions[28].rA(), 29);
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XCTAssertEqual(instructions[28].rS(), 6);
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XCTAssertEqual(instructions[28].uimm(), 8093);
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// .long 0xecff44f6
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// .long 0xf2c1110e
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XCTAssertEqual(instructions[29].operation, Operation::Undefined);
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XCTAssertEqual(instructions[30].operation, Operation::Undefined);
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// stb r21,25915(r6)
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XCTAssertEqual(instructions[31].operation, Operation::stb);
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XCTAssertEqual(instructions[31].rS(), 21);
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XCTAssertEqual(instructions[31].rA(), 6);
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XCTAssertEqual(instructions[31].d(), 25915);
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}
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@end
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@ -58,7 +58,17 @@ Instruction Decoder::decode(uint32_t opcode) {
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Bind(Six(0b001000), subfic);
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Bind(Six(0b001100), addic); Bind(Six(0b001101), addic_);
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Bind(Six(0b001110), addi); Bind(Six(0b001111), addis);
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Bind(Six(0b010000), bcx);
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case Six(0b010000): {
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// This might be a bcx, but check for a valid bo field.
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switch((opcode >> 21) & 0x1f) {
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case 0: case 1: case 2: case 3: case 4: case 5:
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case 8: case 9: case 10: case 11: case 12: case 13:
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case 16: case 17: case 18: case 19: case 20:
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return Instruction(Operation::bcx, opcode);
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default: return Instruction(opcode);
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}
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} break;
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Bind(Six(0b010010), bx);
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Bind(Six(0b010100), rlwimix);
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Bind(Six(0b010101), rlwinmx);
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@ -317,7 +327,9 @@ Instruction Decoder::decode(uint32_t opcode) {
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// std and stdu
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switch(opcode & 0b111111'00'00000000'00000000'000000'11){
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case 0b111110'00'00000000'00000000'000000'00: return Instruction(Operation::std, opcode);
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case 0b111110'00'00000000'00000000'000000'01: return Instruction(Operation::stdu, opcode);
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case 0b111110'00'00000000'00000000'000000'01:
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if(is64bit()) return Instruction(Operation::stdu, opcode);
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return Instruction(opcode);
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}
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// sc
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@ -75,15 +75,16 @@ enum class Operation: uint8_t {
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only the operation has been decoded ahead of time; all other fields are decoded on-demand.
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*/
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struct Instruction {
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const Operation operation = Operation::Undefined;
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const bool is_supervisor = false;
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const uint32_t opcode = 0;
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Operation operation = Operation::Undefined;
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bool is_supervisor = false;
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uint32_t opcode = 0;
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// PowerPC uses a fixed-size instruction word.
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size_t size() {
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int size() {
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return 4;
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}
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Instruction() {}
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Instruction(uint32_t opcode) : opcode(opcode) {}
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Instruction(Operation operation, uint32_t opcode, bool is_supervisor = false) : operation(operation), is_supervisor(is_supervisor), opcode(opcode) {}
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@ -177,7 +178,7 @@ struct Instruction {
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0x0000'0000,
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0xfc00'0000
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};
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const uint32_t value = (opcode & 0x3fff'fffc) | extensions[(opcode >> 26) & 1];
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const uint32_t value = (opcode & 0x03ff'fffc) | extensions[(opcode >> 26) & 1];
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return int32_t(value);
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}
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