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Log memory control meaningfully.

This commit is contained in:
Thomas Harte 2023-01-21 14:13:02 -05:00
parent e289e6e757
commit c9643c4145

View File

@ -312,7 +312,7 @@ template <Analyser::Static::Sega::Target::Model model> class ConcreteMachine:
case 0x00: // i.e. even ports less than 0x40.
if constexpr (is_master_system(model)) {
// TODO: Obey the RAM enable.
LOG("Memory control: " << PADHEX(2) << memory_control_);
LOG("Memory control: " << PADHEX(2) << +memory_control_);
memory_control_ = *cycle.value;
page_cartridge();
}