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mirror of https://github.com/TomHarte/CLK.git synced 2024-11-22 12:33:29 +00:00

Add an SWI count, to aid in logging.

This commit is contained in:
Thomas Harte 2024-03-31 18:18:26 -04:00
parent 31979649c6
commit cc122a7a68

View File

@ -44,7 +44,6 @@ namespace Archimedes {
#ifndef NDEBUG #ifndef NDEBUG
template <InstructionSet::ARM::Model model, typename Executor> template <InstructionSet::ARM::Model model, typename Executor>
struct HackyDebugger { struct HackyDebugger {
void notify(uint32_t address, uint32_t instruction, Executor &executor) { void notify(uint32_t address, uint32_t instruction, Executor &executor) {
pc_history[pc_history_ptr] = address; pc_history[pc_history_ptr] = address;
pc_history_ptr = (pc_history_ptr + 1) % pc_history.size(); pc_history_ptr = (pc_history_ptr + 1) % pc_history.size();
@ -102,6 +101,7 @@ struct HackyDebugger {
) { ) {
if(instruction & 0x2'0000) { if(instruction & 0x2'0000) {
swis.emplace_back(); swis.emplace_back();
swis.back().count = swi_count++;
swis.back().opcode = instruction; swis.back().opcode = instruction;
swis.back().address = executor.pc(); swis.back().address = executor.pc();
swis.back().return_address = executor.registers().pc(4); swis.back().return_address = executor.registers().pc(4);
@ -240,7 +240,7 @@ struct HackyDebugger {
if(executor.registers().pc_status(0) & InstructionSet::ARM::ConditionCode::Overflow) { if(executor.registers().pc_status(0) & InstructionSet::ARM::ConditionCode::Overflow) {
auto info = logger.info(); auto info = logger.info();
info.append("failed swi "); info.append("[%d] Failed swi ", back.count);
if(back.swi_name.empty()) { if(back.swi_name.empty()) {
info.append("&%x", back.opcode & 0xfd'ffff); info.append("&%x", back.opcode & 0xfd'ffff);
} else { } else {
@ -293,8 +293,10 @@ private:
std::array<uint32_t, 75> pc_history; std::array<uint32_t, 75> pc_history;
std::size_t pc_history_ptr = 0; std::size_t pc_history_ptr = 0;
uint32_t instr_count = 0; uint32_t instr_count = 0;
uint32_t swi_count = 0;
struct SWICall { struct SWICall {
uint32_t count;
uint32_t opcode; uint32_t opcode;
uint32_t address; uint32_t address;
uint32_t regs[10]; uint32_t regs[10];