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mirror of https://github.com/TomHarte/CLK.git synced 2026-04-26 03:29:40 +00:00

After much extra logging, corrects destination bank for MVN and MVP.

This commit is contained in:
Thomas Harte
2020-11-15 16:08:29 -05:00
parent 1538a02e18
commit cdacf280e1
2 changed files with 22 additions and 9 deletions
@@ -145,11 +145,11 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
break;
case CycleFetchBlockY:
perform_bus(((instruction_buffer_.value & 0xff00) << 8) | registers_.y.full, &bus_throwaway_, MOS6502Esque::InternalOperationRead);
perform_bus(((instruction_buffer_.value & 0x00ff) << 16) | registers_.y.full, &bus_throwaway_, MOS6502Esque::InternalOperationRead);
break;
case CycleStoreBlockY:
write(((instruction_buffer_.value & 0xff00) << 8) | registers_.y.full, data_buffer_.any_byte());
write(((instruction_buffer_.value & 0x00ff) << 16) | registers_.y.full, data_buffer_.any_byte());
break;
#undef increment_data_address