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https://github.com/TomHarte/CLK.git
synced 2025-01-26 15:32:04 +00:00
Switch to slightly more straightforward presumption of no data wanted.
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parent
9554869886
commit
d6f1ea50a6
@ -29,7 +29,7 @@ Audio::Audio(Chipset &chipset, uint16_t *ram, size_t word_size, float output_rat
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}
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bool Audio::advance_dma(int channel) {
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if(channels_[channel].has_data) {
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if(!channels_[channel].wants_data) {
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return false;
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}
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@ -58,7 +58,7 @@ void Audio::set_volume(int channel, uint16_t volume) {
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void Audio::set_data(int channel, uint16_t data) {
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assert(channel >= 0 && channel < 4);
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channels_[channel].has_data = true;
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channels_[channel].wants_data = false;
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channels_[channel].data = data;
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}
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@ -325,7 +325,7 @@ template <> bool Audio::Channel::transit<
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state = State::PlayingHigh;
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data_latch = data; // i.e. pbufld1
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has_data = false;
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wants_data = true;
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period_counter = period; // i.e. percntrld
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// TODO: volcntrld (see above).
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@ -334,7 +334,7 @@ template <> bool Audio::Channel::transit<
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}
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template <> bool Audio::Channel::output<Audio::Channel::State::Disabled>() {
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if(has_data && !dma_enabled && !interrupt_pending) {
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if(!wants_data && !dma_enabled && !interrupt_pending) {
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return transit<State::Disabled, State::PlayingHigh>();
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}
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@ -355,7 +355,7 @@ template <> bool Audio::Channel::transit<
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Audio::Channel::State::WaitingForDMA>() {
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state = State::WaitingForDMA;
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has_data = false;
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wants_data = true;
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if(length == 1) {
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length_counter = length;
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return true;
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@ -369,7 +369,7 @@ template <> bool Audio::Channel::output<Audio::Channel::State::WaitingForDummyDM
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return transit<State::WaitingForDummyDMA, State::Disabled>();
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}
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if(dma_enabled && has_data) {
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if(dma_enabled && !wants_data) {
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return transit<State::WaitingForDummyDMA, State::WaitingForDMA>();
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}
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@ -386,7 +386,7 @@ template <> bool Audio::Channel::transit<
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state = State::PlayingHigh;
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data_latch = data;
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has_data = false;
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wants_data = true;
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period_counter = period; // i.e. percntrld
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return false;
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@ -397,7 +397,7 @@ template <> bool Audio::Channel::output<Audio::Channel::State::WaitingForDMA>()
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return transit<State::WaitingForDummyDMA, State::Disabled>();
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}
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if(dma_enabled && has_data) {
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if(dma_enabled && !wants_data) {
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return transit<State::WaitingForDummyDMA, State::PlayingHigh>();
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}
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@ -424,7 +424,7 @@ template <> bool Audio::Channel::transit<
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// if lenfin and AUDxON and AUDxDAT, then lencntrld
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// if (not lenfin) and AUDxON and AUDxDAT, then lencount
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// if lenfin and AUDxON and AUDxDAT, then intreq2
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if(dma_enabled && has_data) {
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if(dma_enabled && !wants_data) {
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--length_counter;
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if(!length_counter) {
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length_counter = length;
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@ -465,7 +465,7 @@ template <> bool Audio::Channel::transit<
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return true;
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} else {
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data_latch = data; // i.e. pbufld2
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has_data = false; // AUDxDR
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wants_data = true; // AUDxDR
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}
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if(dma_enabled && will_request_interrupt) {
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@ -67,7 +67,7 @@ class Audio: public DMADevice<4> {
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// The data latch plus a count of unused samples
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// in the latch, which will always be 0, 1 or 2.
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uint16_t data = 0x0000;
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bool has_data = false;
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bool wants_data = false;
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uint16_t data_latch = 0x0000;
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// Number of words remaining in DMA data.
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