6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-09-28 09:54:49 +00:00
Code Issues Projects Releases Wiki Activity

Add appropriate exclusions for JSR, JMP, Scc.

Browse Source
This commit is contained in:
Thomas Harte 2022-04-20 16:56:26 -04:00
parent a4e440527b
commit dc16928f74
2 changed files with 77 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
InstructionSets/68k/Decoder.cpp
View File

@ -301,6 +301,31 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
case AddressingMode::None:
return Preinstruction();
}
case OpT(Operation::JSR): case OpT(Operation::JMP):
switch(original.mode<0>()) {
default: return original;
case AddressingMode::DataRegisterDirect:
case AddressingMode::AddressRegisterDirect:
case AddressingMode::AddressRegisterIndirectWithPostincrement:
case AddressingMode::AddressRegisterIndirectWithPredecrement:
case AddressingMode::ImmediateData:
case AddressingMode::None:
return Preinstruction();
}
case OpT(Operation::Scc):
switch(original.mode<0>()) {
default: return original;
case AddressingMode::AddressRegisterDirect:
case AddressingMode::ImmediateData:
case AddressingMode::ProgramCounterIndirectWithDisplacement:
case AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement:
case AddressingMode::None:
return Preinstruction();
}
}
}

52
OSBindings/Mac/Clock SignalTests/m68kDecoderTests.mm
View File

@ -149,6 +149,58 @@ template <int index> NSString *operand(Preinstruction instruction) {
case Operation::TSTw: instruction = @"TST.w"; break;
case Operation::TSTl: instruction = @"TST.l"; break;
case Operation::JMP: instruction = @"JMP"; break;
case Operation::JSR: instruction = @"JSR"; break;
case Operation::RTS: instruction = @"RTS"; break;
case Operation::DBcc: instruction = @"DBcc"; break;
case Operation::Scc: instruction = @"Scc"; break;
/*
TODO:
Bccb, Bccl, Bccw,
BSRb, BSRl, BSRw,
CLRb, CLRw, CLRl,
NEGXb, NEGXw, NEGXl,
NEGb, NEGw, NEGl,
ASLb, ASLw, ASLl, ASLm,
ASRb, ASRw, ASRl, ASRm,
LSLb, LSLw, LSLl, LSLm,
LSRb, LSRw, LSRl, LSRm,
ROLb, ROLw, ROLl, ROLm,
RORb, RORw, RORl, RORm,
ROXLb, ROXLw, ROXLl, ROXLm,
ROXRb, ROXRw, ROXRl, ROXRm,
MOVEMl, MOVEMw,
MOVEPl, MOVEPw,
ANDb, ANDw, ANDl,
EORb, EORw, EORl,
NOTb, NOTw, NOTl,
ORb, ORw, ORl,
MULU, MULS,
DIVU, DIVS,
RTE, RTR,
TRAP, TRAPV,
CHK,
EXG, SWAP,
TAS,
EXTbtow, EXTwtol,
LINKw, UNLINK,
STOP, RESET,
*/
// For now, skip any unmapped operations.
default: continue;
}