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Fix 65c02 modify cycles: read/read/write, not read/write/write.

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This commit is contained in:
Thomas Harte
2025-10-24 13:30:10 -04:00
parent aeabd5f113
commit e4fe127444
2 changed files with 13 additions and 5 deletions
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Processors/6502Mk2/Decoder.hpp
+3 -3
View File
@@ -115,7 +115,7 @@ constexpr Type type_of(const Operation operation) {
case Operation::LDY: case Operation::LAX:
case Operation::ARR: case Operation::SBX: case Operation::LXA:
case Operation::ANE: case Operation::ANC: case Operation::LAS:
case Operation::NOP:
case Operation::NOP: case Operation::FastNOP:
return Type::Read;
case Operation::STA: case Operation::STX: case Operation::STY:
@@ -470,12 +470,12 @@ struct Decoder<model, std::enable_if_t<model == Model::Synertek65C02>> {
case 0xc3: return {Implied, Operation::FastNOP};
case 0xe3: return {Implied, Operation::FastNOP};
case 0x89: return {Immediate, Operation::BITNoNV};
case 0x04: return {Zero, Operation::TSB};
case 0x64: return {Zero, Operation::STZ};
case 0x9e: return {AbsoluteIndexed, Operation::STZ};
case 0x89: return {Immediate, Operation::BITNoNV};
case 0x0b: return {Implied, Operation::FastNOP};
case 0x2b: return {Implied, Operation::FastNOP};
case 0x4b: return {Implied, Operation::FastNOP};
Processors/6502Mk2/Implementation/6502.hpp
+10 -2
View File
@@ -102,7 +102,11 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
}
// Modify stall.
access(BusOperation::Write, ZeroPage(Storage::address_.halves.low), Storage::operand_);
access(
is_65c02(model) ? BusOperation::Read : BusOperation::Write,
ZeroPage(Storage::address_.halves.low),
Storage::operand_
);
// Write.
access_zero_write:
@@ -126,7 +130,11 @@ void Processor<model, Traits>::run_for(const Cycles cycles) {
}
// Modify stall.
access(BusOperation::Write, Literal(Storage::address_.full), Storage::operand_);
access(
is_65c02(model) ? BusOperation::Read : BusOperation::Write,
Literal(Storage::address_.full),
Storage::operand_
);
// Write.
access_absolute_write: