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Provide card's SCSI ID.

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This commit is contained in:
Thomas Harte 2022-08-23 15:05:36 -04:00
parent f4c242d5e9
commit ea4bf5f31a
3 changed files with 33 additions and 16 deletions
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40
Components/5380/ncr5380.cpp
View File

@ -8,6 +8,10 @@
#include "ncr5380.hpp"
#ifndef NDEBUG
#define NDEBUG
#endif
#include "../../Outputs/Log.hpp"
using namespace NCR::NCR5380;
@ -28,7 +32,7 @@ NCR5380::NCR5380(SCSI::Bus &bus, int clock_rate) :
void NCR5380::write(int address, uint8_t value, bool) {
switch(address & 7) {
case 0:
// LOG("[SCSI 0] Set current SCSI bus state to " << PADHEX(2) << int(value));
LOG("[SCSI 0] Set current SCSI bus state to " << PADHEX(2) << int(value));
data_bus_ = value;
if(dma_request_ && dma_operation_ == DMAOperation::Send) {
@ -41,7 +45,7 @@ void NCR5380::write(int address, uint8_t value, bool) {
break;
case 1: {
// LOG("[SCSI 1] Initiator command register set: " << PADHEX(2) << int(value));
LOG("[SCSI 1] Initiator command register set: " << PADHEX(2) << int(value));
initiator_command_ = value;
bus_output_ &= ~(Line::Reset | Line::Acknowledge | Line::Busy | Line::SelectTarget | Line::Attention);
@ -57,7 +61,7 @@ void NCR5380::write(int address, uint8_t value, bool) {
} break;
case 2:
// LOG("[SCSI 2] Set mode: " << PADHEX(2) << int(value));
LOG("[SCSI 2] Set mode: " << PADHEX(2) << int(value));
mode_ = value;
// bit 7: 1 = use block mode DMA mode (if DMA mode is also enabled)
@ -92,27 +96,27 @@ void NCR5380::write(int address, uint8_t value, bool) {
break;
case 3: {
// LOG("[SCSI 3] Set target command: " << PADHEX(2) << int(value));
LOG("[SCSI 3] Set target command: " << PADHEX(2) << int(value));
target_command_ = value;
update_control_output();
} break;
case 4:
// LOG("[SCSI 4] Set select enabled: " << PADHEX(2) << int(value));
LOG("[SCSI 4] Set select enabled: " << PADHEX(2) << int(value));
break;
case 5:
// LOG("[SCSI 5] Start DMA send: " << PADHEX(2) << int(value));
LOG("[SCSI 5] Start DMA send: " << PADHEX(2) << int(value));
dma_operation_ = DMAOperation::Send;
break;
case 6:
// LOG("[SCSI 6] Start DMA target receive: " << PADHEX(2) << int(value));
LOG("[SCSI 6] Start DMA target receive: " << PADHEX(2) << int(value));
dma_operation_ = DMAOperation::TargetReceive;
break;
case 7:
// LOG("[SCSI 7] Start DMA initiator receive: " << PADHEX(2) << int(value));
LOG("[SCSI 7] Start DMA initiator receive: " << PADHEX(2) << int(value));
dma_operation_ = DMAOperation::InitiatorReceive;
break;
}
@ -136,7 +140,7 @@ void NCR5380::write(int address, uint8_t value, bool) {
uint8_t NCR5380::read(int address, bool) {
switch(address & 7) {
case 0:
// LOG("[SCSI 0] Get current SCSI bus state: " << PADHEX(2) << (bus_.get_state() & 0xff));
LOG("[SCSI 0] Get current SCSI bus state: " << PADHEX(2) << (bus_.get_state() & 0xff));
if(dma_request_ && dma_operation_ == DMAOperation::InitiatorReceive) {
dma_acknowledge_ = true;
@ -147,7 +151,7 @@ uint8_t NCR5380::read(int address, bool) {
return uint8_t(bus_.get_state());
case 1:
// LOG("[SCSI 1] Initiator command register get: " << (arbitration_in_progress_ ? 'p' : '-') << (lost_arbitration_ ? 'l' : '-'));
LOG("[SCSI 1] Initiator command register get: " << (arbitration_in_progress_ ? 'p' : '-') << (lost_arbitration_ ? 'l' : '-'));
return
// Bits repeated as they were set.
(initiator_command_ & ~0x60) |
@ -159,11 +163,11 @@ uint8_t NCR5380::read(int address, bool) {
(lost_arbitration_ ? 0x20 : 0x00);
case 2:
// LOG("[SCSI 2] Get mode");
LOG("[SCSI 2] Get mode");
return mode_;
case 3:
// LOG("[SCSI 3] Get target command");
LOG("[SCSI 3] Get target command");
return target_command_;
case 4: {
@ -177,7 +181,7 @@ uint8_t NCR5380::read(int address, bool) {
((bus_state & Line::Input) ? 0x04 : 0x00) |
((bus_state & Line::SelectTarget) ? 0x02 : 0x00) |
((bus_state & Line::Parity) ? 0x01 : 0x00);
// LOG("[SCSI 4] Get current bus state: " << PADHEX(2) << int(result));
LOG("[SCSI 4] Get current bus state: " << PADHEX(2) << int(result));
return result;
}
@ -196,16 +200,16 @@ uint8_t NCR5380::read(int address, bool) {
/* b2 = busy error */
((bus_state & Line::Attention) ? 0x02 : 0x00) |
((bus_state & Line::Acknowledge) ? 0x01 : 0x00);
// LOG("[SCSI 5] Get bus and status: " << PADHEX(2) << int(result));
LOG("[SCSI 5] Get bus and status: " << PADHEX(2) << int(result));
return result;
}
case 6:
// LOG("[SCSI 6] Get input data");
LOG("[SCSI 6] Get input data");
return 0xff;
case 7:
// LOG("[SCSI 7] Reset parity/interrupt");
LOG("[SCSI 7] Reset parity/interrupt");
return 0xff;
}
return 0;
@ -316,3 +320,7 @@ void NCR5380::set_execution_state(ExecutionState state) {
state_ = state;
if(state != ExecutionState::PerformingDMA) dma_operation_ = DMAOperation::Ready;
}
size_t NCR5380::scsi_id() {
return device_id_;
}

3
Components/5380/ncr5380.hpp
View File

@ -30,6 +30,9 @@ class NCR5380 final: public SCSI::Bus::Observer {
/*! Reads from @c address. */
uint8_t read(int address, bool dma_acknowledge = false);
/*! @returns The SCSI ID assigned to this device. */
size_t scsi_id();
private:
SCSI::Bus &bus_;

6
Machines/Apple/AppleII/SCSICard.cpp
View File

@ -93,6 +93,12 @@ void SCSICard::perform_bus_operation(Select select, bool is_read, uint16_t addre
}
break;
case 0x9:
if(is_read) {
*value = uint8_t(ncr5380_.scsi_id());
}
break;
case 0xa:
// RAM and ROM select.
if(!is_read) {