6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-26 23:52:26 +00:00
Code Issues Projects Releases Wiki Activity

Converts the prefetch queue into a 32-bit quantity.

Browse Source
This commit is contained in:
Thomas Harte 2019-03-19 21:33:52 -04:00
parent 21cb7307d0
commit eeb161ec51
3 changed files with 14 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
Processors/68000/Implementation/68000Implementation.hpp
View File

@ -45,7 +45,7 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
case BusStep::Action::IncrementProgramCounter: program_counter_.full += 2; break;
case BusStep::Action::AdvancePrefetch:
prefetch_queue_[0] = prefetch_queue_[1];
prefetch_queue_.halves.high = prefetch_queue_.halves.low;
break;
}
@ -69,7 +69,7 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
// TODO: unless an interrupt is pending, or the trap flag is set.
const uint16_t next_instruction = prefetch_queue_[0].full;
const uint16_t next_instruction = prefetch_queue_.halves.high;
if(!instructions[next_instruction].micro_operations) {
// TODO: once all instructions are implemnted, this should be an instruction error.
std::cerr << "68000 Abilities exhausted; can't manage instruction " << std::hex << next_instruction << std::endl;
@ -205,16 +205,16 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
break;
case int(MicroOp::Action::CalcD16An) | MicroOp::SourceMask:
effective_address_[0] = int16_t(prefetch_queue_[0].full) + active_program_->source->full;
effective_address_[0] = int16_t(prefetch_queue_.halves.high) + active_program_->source->full;
break;
case int(MicroOp::Action::CalcD16An) | MicroOp::DestinationMask:
effective_address_[1] = int16_t(prefetch_queue_[0].full) + active_program_->destination->full;
effective_address_[1] = int16_t(prefetch_queue_.halves.high) + active_program_->destination->full;
break;
case int(MicroOp::Action::CalcD16An) | MicroOp::SourceMask | MicroOp::DestinationMask:
effective_address_[0] = int16_t(prefetch_queue_[0].full) + active_program_->source->full;
effective_address_[1] = int16_t(prefetch_queue_[1].full) + active_program_->destination->full;
effective_address_[0] = int16_t(prefetch_queue_.halves.high) + active_program_->source->full;
effective_address_[1] = int16_t(prefetch_queue_.halves.low) + active_program_->destination->full;
break;
// TODO: permit as below for DestinationMask and SourceMask|DestinationMask; would prefer to test first.
@ -230,26 +230,26 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
} \
}
case int(MicroOp::Action::CalcD8AnXn) | MicroOp::SourceMask: {
CalculateD8AnXn(prefetch_queue_[0], active_program_->source, effective_address_[0]);
CalculateD8AnXn(prefetch_queue_.halves.high, active_program_->source, effective_address_[0]);
} break;
case int(MicroOp::Action::CalcD8AnXn) | MicroOp::DestinationMask: {
CalculateD8AnXn(prefetch_queue_[0], active_program_->destination, effective_address_[1]);
CalculateD8AnXn(prefetch_queue_.halves.high, active_program_->destination, effective_address_[1]);
} break;
case int(MicroOp::Action::CalcD8AnXn) | MicroOp::SourceMask | MicroOp::DestinationMask: {
CalculateD8AnXn(prefetch_queue_[0], active_program_->source, effective_address_[0]);
CalculateD8AnXn(prefetch_queue_[1], active_program_->destination, effective_address_[1]);
CalculateD8AnXn(prefetch_queue_.halves.high, active_program_->source, effective_address_[0]);
CalculateD8AnXn(prefetch_queue_.halves.low, active_program_->destination, effective_address_[1]);
} break;
#undef CalculateD8AnXn
case int(MicroOp::Action::AssembleWordFromPrefetch) | MicroOp::SourceMask:
bus_data_[0] = (prefetch_queue_[0] << 16) | prefetch_queue_[1];
bus_data_[0] = prefetch_queue_.full;
break;
case int(MicroOp::Action::AssembleWordFromPrefetch) | MicroOp::DestinationMask:
bus_data_[1] = (prefetch_queue_[0] << 16) | prefetch_queue_[1];
bus_data_[1] = prefetch_queue_.full;
break;
}

2
Processors/68000/Implementation/68000Storage.cpp
View File

@ -128,7 +128,7 @@ struct ProcessorStorageConstructor {
step.microcycle.length = HalfCycles(5);
step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram;
step.microcycle.address = &storage_.program_counter_.full;
step.microcycle.value = &storage_.prefetch_queue_[1];
step.microcycle.value = &storage_.prefetch_queue_.halves.low;
step.action = Action::AdvancePrefetch;
steps.push_back(step);

2
Processors/68000/Implementation/68000Storage.hpp
View File

@ -21,7 +21,7 @@ class ProcessorStorage {
RegisterPair32 stack_pointers_[2]; // [0] = user stack pointer; [1] = supervisor; the values from here
// are copied into/out of address_[7] upon mode switches.
RegisterPair16 prefetch_queue_[2];
RegisterPair32 prefetch_queue_; // Each word will go into the low part of the word, then proceed upward.
bool dtack_ = true;
// Various status bits.