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Add tests for RTE, RTR, TRAP, TRAPV, CHK.

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This commit is contained in:
Thomas Harte 2022-04-22 10:06:39 -04:00
parent 06fb502047
commit efeee5160e
3 changed files with 18 additions and 10 deletions
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1
InstructionSets/68k/Decoder.cpp
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@ -411,6 +411,7 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
case OpT(Operation::DIVU): case OpT(Operation::DIVS):
case OpT(Operation::MULU): case OpT(Operation::MULS):
case OpT(Operation::CHK):
switch(original.mode<0>()) {
default: return original;

13
InstructionSets/68k/Instruction.hpp
View File

@ -142,6 +142,7 @@ constexpr int8_t quick(uint16_t instruction) {
case Operation::Bccb:
case Operation::BSRb:
case Operation::MOVEq: return int8_t(instruction);
case Operation::TRAP: return int8_t(instruction & 15);
default: {
int8_t value = (instruction >> 9) & 7;
value |= (value - 1)&8;
@ -151,10 +152,14 @@ constexpr int8_t quick(uint16_t instruction) {
}
constexpr int8_t quick(Operation op, uint16_t instruction) {
if(op == Operation::MOVEq || op == Operation::Bccb || op == Operation::BSRb) {
return quick<Operation::MOVEq>(instruction);
} else {
// ADDw is arbitrary; anything other than MOVEq will do.
switch(op) {
case Operation::MOVEq: return quick<Operation::MOVEq>(instruction);
case Operation::Bccb: return quick<Operation::Bccb>(instruction);
case Operation::BSRb: return quick<Operation::BSRb>(instruction);
case Operation::TRAP: return quick<Operation::TRAP>(instruction);
default:
// ADDw is arbitrary; anything other than those listed above will do.
return quick<Operation::ADDw>(instruction);
}
}

12
OSBindings/Mac/Clock SignalTests/m68kDecoderTests.mm
View File

@ -246,14 +246,16 @@ template <int index> NSString *operand(Preinstruction instruction, uint16_t opco
case Operation::DIVU: instruction = @"DIVU"; break;
case Operation::DIVS: instruction = @"DIVS"; break;
case Operation::RTE: instruction = @"RTE"; break;
case Operation::RTR: instruction = @"RTR"; break;
case Operation::TRAP: instruction = @"TRAP"; break;
case Operation::TRAPV: instruction = @"TRAPV"; break;
case Operation::CHK: instruction = @"CHK"; break;
/*
TODO:
RTE, RTR,
TRAP, TRAPV,
CHK,
EXG, SWAP,
TAS,