mirror of
https://github.com/TomHarte/CLK.git
synced 2024-12-23 20:29:42 +00:00
Breaks Chipset::perform into read and write.
This allows each to call the other when a read occurs of a write-only address, and vice versa.
This commit is contained in:
Thomas Harte
parent
c4055fde97
commit
f118891970
@ -808,12 +808,16 @@ void Chipset::update_interrupts() {
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void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
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using Microcycle = CPU::MC68000::Microcycle;
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#define RW(address) address | ((cycle.operation & Microcycle::Read) << 12)
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#define Read(address) address | (Microcycle::Read << 12)
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#define Write(address) address
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const uint32_t register_address = *cycle.address & 0x1fe;
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if(cycle.operation & Microcycle::Read) {
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cycle.set_value16(read(register_address));
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} else {
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write(register_address, cycle.value16());
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}
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}
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void Chipset::write(uint32_t address, uint16_t value) {
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#define ApplySetClear(target, mask) { \
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const uint16_t value = cycle.value16(); \
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if(value & 0x8000) { \
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target |= (value & mask); \
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} else { \
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@ -821,40 +825,15 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
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} \
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}
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const uint32_t register_address = *cycle.address & 0x1fe;
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switch(RW(register_address)) {
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switch(address) {
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default:
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LOG("Unimplemented chipset " << (cycle.operation & Microcycle::Read ? "read" : "write") << " " << PADHEX(6) << *cycle.address);
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if(cycle.operation & Microcycle::Read) {
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cycle.set_value16(0xffff);
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}
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// If there was nothing to write, perform a throwaway read.
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read(address);
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break;
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// Raster position.
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case Read(0x004): { // VPOSR; b15 = LOF, b0 = b8 of y position.
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const uint16_t position = uint16_t(y_ >> 8);
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cycle.set_value16(
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position |
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(is_long_field_ ? 0x8000 : 0x0000)
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);
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// b8–b14 should be:
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// 00 for PAL Agnus or fat Agnus
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// 10 for NTSC Agnus or fat Agnus
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// 20 for PAL high-res
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// 30 for NTSC high-res
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} break;
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case Read(0x006): { // VHPOSR; b0–b7 = horizontal; b8–b15 = low bits of vertical position.
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const uint16_t position = uint16_t(((line_cycle_ >> 1) & 0x00ff) | (y_ << 8));
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cycle.set_value16(position);
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} break;
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case Read(0x00e): { // CLXDAT
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cycle.set_value16(collisions_);
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collisions_ = 0;
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} break;
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case Write(0x098): // CLXCON
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collisions_flags_ = cycle.value16();
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case 0x098: // CLXCON
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collisions_flags_ = value;
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// Produce appropriate bitfield manipulation values, including shuffling the bits.
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playfield_collision_mask_ = bitplane_swizzle(uint32_t((collisions_flags_ & 0xfc0) >> 6));
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@ -864,42 +843,29 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
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playfield_collision_complement_ |= (playfield_collision_complement_ << 8) | (playfield_collision_complement_ << 16) | (playfield_collision_complement_ << 24);
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break;
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case Write(0x02a): // VPOSW
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case 0x02a: // VPOSW
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LOG("TODO: write vertical position high " << PADHEX(4) << cycle.value16());
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break;
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case Write(0x02c): { // VHPOSW
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case 0x02c: // VHPOSW
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LOG("TODO: write vertical position low " << PADHEX(4) << cycle.value16());
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const uint16_t value = cycle.value16();
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is_long_field_ = value & 0x8000;
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} break;
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break;
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// Joystick/mouse input.
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case Read(0x00a): // JOY0DAT
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cycle.set_value16(mouse_.get_position());
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break;
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case Read(0x00c): // JOY1DAT
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cycle.set_value16(joystick(0).get_position());
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break;
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case Write(0x034): // POTGO
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case 0x034: // POTGO
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// LOG("TODO: pot port start");
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break;
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case Read(0x016): // POTGOR / POTINP
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// LOG("TODO: pot port read");
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cycle.set_value16(0xff00);
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break;
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// Disk DMA and control.
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case Write(0x020): disk_.set_pointer<0, 16>(cycle.value16()); break; // DSKPTH
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case Write(0x022): disk_.set_pointer<0, 0>(cycle.value16()); break; // DSKPTL
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case Write(0x024): disk_.set_length(cycle.value16()); break; // DSKLEN
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case 0x020: disk_.set_pointer<0, 16>(value); break; // DSKPTH
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case 0x022: disk_.set_pointer<0, 0>(value); break; // DSKPTL
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case 0x024: disk_.set_length(value); break; // DSKLEN
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case Write(0x026): // DSKDAT
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case 0x026: // DSKDAT
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LOG("TODO: disk DMA; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
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break;
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case Write(0x09e): // ADKCON
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case 0x09e: // ADKCON
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LOG("Write disk control");
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ApplySetClear(paula_disk_control_, 0x7fff);
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@ -907,188 +873,148 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
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disk_.set_control(paula_disk_control_);
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audio_.set_modulation_flags(paula_disk_control_);
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break;
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case Read(0x010): // ADKCONR
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LOG("Read disk control");
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cycle.set_value16(paula_disk_control_);
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break;
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case Write(0x07e): // DSKSYNC
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disk_controller_.set_sync_word(cycle.value16());
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break;
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case Read(0x01a): // DSKBYTR
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LOG("TODO: disk status");
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assert(false); // Not yet implemented.
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case 0x07e: // DSKSYNC
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disk_controller_.set_sync_word(value);
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break;
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// Refresh.
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case Write(0x028): // REFPTR
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case 0x028: // REFPTR
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LOG("TODO (maybe): refresh; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
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break;
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// Serial port.
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case Read(0x018): // SERDATR
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LOG("TODO: serial data and status");
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cycle.set_value16(0x3000); // i.e. transmit buffer empty.
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break;
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case Write(0x030): // SERDAT
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case 0x030: // SERDAT
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LOG("TODO: serial data: " << PADHEX(4) << cycle.value16());
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break;
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case Write(0x032): // SERPER
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case 0x032: // SERPER
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LOG("TODO: serial control: " << PADHEX(4) << cycle.value16());
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serial_.set_control(cycle.value16());
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serial_.set_control(value);
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break;
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// DMA management.
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case Read(0x002): // DMACONR
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cycle.set_value16(dma_control_ | blitter_.get_status());
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break;
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case Write(0x096): // DMACON
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case 0x096: // DMACON
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ApplySetClear(dma_control_, 0x1fff);
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audio_.set_channel_enables(dma_control_);
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break;
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// Interrupts.
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case Write(0x09a): // INTENA
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case 0x09a: // INTENA
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ApplySetClear(interrupt_enable_, 0x7fff);
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update_interrupts();
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break;
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case Read(0x01c): // INTENAR
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cycle.set_value16(interrupt_enable_);
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break;
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case Write(0x09c): // INTREQ
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case 0x09c: // INTREQ
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ApplySetClear(interrupt_requests_, 0x7fff);
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update_interrupts();
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break;
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case Read(0x01e): // INTREQR
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cycle.set_value16(interrupt_requests_);
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break;
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// Display management.
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case Write(0x08e): { // DIWSTRT
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const uint16_t value = cycle.value16();
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case 0x08e: // DIWSTRT
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display_window_start_[0] = value & 0xff;
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display_window_start_[1] = value >> 8;
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} break;
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case Write(0x090): { // DIWSTOP
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const uint16_t value = cycle.value16();
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break;
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case 0x090: // DIWSTOP
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display_window_stop_[0] = 0x100 | (value & 0xff);
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display_window_stop_[1] = value >> 8;
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display_window_stop_[1] |= ((value >> 7) & 0x100) ^ 0x100;
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} break;
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case Write(0x092): // DDFSTRT
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if(fetch_window_[0] != cycle.value16()) {
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break;
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case 0x092: // DDFSTRT
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if(fetch_window_[0] != value) {
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LOG("Fetch window start set to " << std::dec << cycle.value16());
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}
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fetch_window_[0] = cycle.value16();
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fetch_window_[0] = value;
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break;
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case Write(0x094): // DDFSTOP
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case 0x094: // DDFSTOP
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// TODO: something in my interpretation of ddfstart and ddfstop
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// means a + 8 is needed below for high-res displays. Investigate.
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if(fetch_window_[1] != cycle.value16()) {
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if(fetch_window_[1] != value) {
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LOG("Fetch window stop set to " << std::dec << fetch_window_[1]);
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}
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fetch_window_[1] = cycle.value16();
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fetch_window_[1] = value;
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break;
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// Bitplanes.
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case Write(0x0e0): bitplanes_.set_pointer<0, 16>(cycle.value16()); break; // BPL1PTH
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case Write(0x0e2): bitplanes_.set_pointer<0, 0>(cycle.value16()); break; // BPL1PTL
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case Write(0x0e4): bitplanes_.set_pointer<1, 16>(cycle.value16()); break; // BPL2PTH
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case Write(0x0e6): bitplanes_.set_pointer<1, 0>(cycle.value16()); break; // BPL2PTL
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case Write(0x0e8): bitplanes_.set_pointer<2, 16>(cycle.value16()); break; // BPL3PTH
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case Write(0x0ea): bitplanes_.set_pointer<2, 0>(cycle.value16()); break; // BPL3PTL
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case Write(0x0ec): bitplanes_.set_pointer<3, 16>(cycle.value16()); break; // BPL4PTH
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case Write(0x0ee): bitplanes_.set_pointer<3, 0>(cycle.value16()); break; // BPL4PTL
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case Write(0x0f0): bitplanes_.set_pointer<4, 16>(cycle.value16()); break; // BPL5PTH
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case Write(0x0f2): bitplanes_.set_pointer<4, 0>(cycle.value16()); break; // BPL5PTL
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case Write(0x0f4): bitplanes_.set_pointer<5, 16>(cycle.value16()); break; // BPL6PTH
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case Write(0x0f6): bitplanes_.set_pointer<5, 0>(cycle.value16()); break; // BPL6PTL
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case 0x0e0: bitplanes_.set_pointer<0, 16>(value); break; // BPL1PTH
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case 0x0e2: bitplanes_.set_pointer<0, 0>(value); break; // BPL1PTL
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case 0x0e4: bitplanes_.set_pointer<1, 16>(value); break; // BPL2PTH
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case 0x0e6: bitplanes_.set_pointer<1, 0>(value); break; // BPL2PTL
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case 0x0e8: bitplanes_.set_pointer<2, 16>(value); break; // BPL3PTH
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case 0x0ea: bitplanes_.set_pointer<2, 0>(value); break; // BPL3PTL
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case 0x0ec: bitplanes_.set_pointer<3, 16>(value); break; // BPL4PTH
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case 0x0ee: bitplanes_.set_pointer<3, 0>(value); break; // BPL4PTL
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case 0x0f0: bitplanes_.set_pointer<4, 16>(value); break; // BPL5PTH
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case 0x0f2: bitplanes_.set_pointer<4, 0>(value); break; // BPL5PTL
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case 0x0f4: bitplanes_.set_pointer<5, 16>(value); break; // BPL6PTH
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case 0x0f6: bitplanes_.set_pointer<5, 0>(value); break; // BPL6PTL
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case Write(0x100): { // BPLCON0
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const auto value = cycle.value16();
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case 0x100: // BPLCON0
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bitplanes_.set_control(value);
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is_high_res_ = value & 0x8000;
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hold_and_modify_ = value & 0x0800;
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dual_playfields_ = value & 0x0400;
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interlace_ = value & 0x0004;
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// LOG("New video control at " << std::dec << y_ << "; high res: " << is_high_res_ << " HAM: " << hold_and_modify_ << " dual: " << dual_playfields_ << " interlace: " << interlace_);
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} break;
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case Write(0x102): { // BPLCON1
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const uint8_t delay = cycle.value8_low();
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odd_delay_ = delay & 0x0f;
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even_delay_ = delay >> 4;
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} break;
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case Write(0x104): { // BPLCON2
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const auto value = cycle.value16();
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break;
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case 0x102: // BPLCON1
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odd_delay_ = value & 0x0f;
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even_delay_ = (value >> 4) & 0x0f;
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break;
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case 0x104: // BPLCON2
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odd_priority_ = value & 7; // i.e. "Playfield 1"; planes 1, 3 and 5.
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even_priority_ = (value >> 3) & 7; // i.e. "Playfield 2"; planes 2, 4 and 6.
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even_over_odd_ = value & 0x40;
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} break;
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break;
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case Write(0x106): // BPLCON3 (ECS)
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case 0x106: // BPLCON3 (ECS)
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LOG("TODO: Bitplane control; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
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break;
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case Write(0x108): bitplanes_.set_modulo<0>(cycle.value16()); break; // BPL1MOD
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case Write(0x10a): bitplanes_.set_modulo<1>(cycle.value16()); break; // BPL2MOD
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case 0x108: bitplanes_.set_modulo<0>(value); break; // BPL1MOD
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case 0x10a: bitplanes_.set_modulo<1>(value); break; // BPL2MOD
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case Write(0x110):
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case Write(0x112):
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case Write(0x114):
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case Write(0x116):
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case Write(0x118):
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case Write(0x11a):
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LOG("TODO: Bitplane data; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
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break;
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case Read(0x110): case Read(0x112): case Read(0x114): case Read(0x116):
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case Read(0x118): case Read(0x11a):
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cycle.set_value16(0xffff);
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LOG("Invalid read at " << PADHEX(6) << *cycle.address);
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case 0x110:
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case 0x112:
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case 0x114:
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case 0x116:
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case 0x118:
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case 0x11a:
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LOG("TODO: Bitplane data; " << PADHEX(4) << value << " to " << *cycle.address);
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break;
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// Blitter.
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case Read(0x040): blitter_.set_control(0, 0xffff); break; // UGH. Have fallen into quite a hole here with my
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case Read(0x042): blitter_.set_control(1, 0xffff); break; // Read/Write macros. TODO: some sort of canonical decode?
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// Templatey to hit the usual Read/Write cases first?
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case Write(0x040): blitter_.set_control(0, cycle.value16()); break;
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case Write(0x042): blitter_.set_control(1, cycle.value16()); break;
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case Write(0x044): blitter_.set_first_word_mask(cycle.value16()); break;
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case Write(0x046): blitter_.set_last_word_mask(cycle.value16()); break;
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case 0x040: blitter_.set_control(0, value); break;
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case 0x042: blitter_.set_control(1, value); break;
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case 0x044: blitter_.set_first_word_mask(value); break;
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case 0x046: blitter_.set_last_word_mask(value); break;
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case Write(0x048): blitter_.set_pointer<2, 16>(cycle.value16()); break;
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case Write(0x04a): blitter_.set_pointer<2, 0>(cycle.value16()); break;
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case Write(0x04c): blitter_.set_pointer<1, 16>(cycle.value16()); break;
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case Write(0x04e): blitter_.set_pointer<1, 0>(cycle.value16()); break;
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case Write(0x050): blitter_.set_pointer<0, 16>(cycle.value16()); break;
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case Write(0x052): blitter_.set_pointer<0, 0>(cycle.value16()); break;
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case Write(0x054): blitter_.set_pointer<3, 16>(cycle.value16()); break;
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case Write(0x056): blitter_.set_pointer<3, 0>(cycle.value16()); break;
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case 0x048: blitter_.set_pointer<2, 16>(value); break;
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case 0x04a: blitter_.set_pointer<2, 0>(value); break;
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case 0x04c: blitter_.set_pointer<1, 16>(value); break;
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case 0x04e: blitter_.set_pointer<1, 0>(value); break;
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case 0x050: blitter_.set_pointer<0, 16>(value); break;
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case 0x052: blitter_.set_pointer<0, 0>(value); break;
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case 0x054: blitter_.set_pointer<3, 16>(value); break;
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case 0x056: blitter_.set_pointer<3, 0>(value); break;
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case Write(0x058): blitter_.set_size(cycle.value16()); break;
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case Write(0x05a): blitter_.set_minterms(cycle.value16()); break;
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// case Write(0x05c): blitter_.set_vertical_size(cycle.value16()); break;
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// case Write(0x05e): blitter_.set_horizontal_size(cycle.value16()); break;
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case 0x058: blitter_.set_size(value); break;
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case 0x05a: blitter_.set_minterms(value); break;
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case Write(0x060): blitter_.set_modulo<2>(cycle.value16()); break;
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case Write(0x062): blitter_.set_modulo<1>(cycle.value16()); break;
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case Write(0x064): blitter_.set_modulo<0>(cycle.value16()); break;
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case Write(0x066): blitter_.set_modulo<3>(cycle.value16()); break;
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case 0x060: blitter_.set_modulo<2>(value); break;
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case 0x062: blitter_.set_modulo<1>(value); break;
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case 0x064: blitter_.set_modulo<0>(value); break;
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case 0x066: blitter_.set_modulo<3>(value); break;
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case Write(0x070): blitter_.set_data(2, cycle.value16()); break;
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case Write(0x072): blitter_.set_data(1, cycle.value16()); break;
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case Write(0x074): blitter_.set_data(0, cycle.value16()); break;
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case 0x070: blitter_.set_data(2, value); break;
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case 0x072: blitter_.set_data(1, value); break;
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case 0x074: blitter_.set_data(0, value); break;
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// Audio.
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#define Audio(index, pointer) \
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||||
case Write(pointer + 0): audio_.set_pointer<index, 16>(cycle.value16()); break; \
|
||||
case Write(pointer + 2): audio_.set_pointer<index, 0>(cycle.value16()); break; \
|
||||
case Write(pointer + 4): audio_.set_length(index, cycle.value16()); break; \
|
||||
case Write(pointer + 6): audio_.set_period(index, cycle.value16()); break; \
|
||||
case Write(pointer + 8): audio_.set_volume(index, cycle.value16()); break; \
|
||||
case Write(pointer + 10): audio_.set_data(index, cycle.value16()); break; \
|
||||
case pointer + 0: audio_.set_pointer<index, 16>(value); break; \
|
||||
case pointer + 2: audio_.set_pointer<index, 0>(value); break; \
|
||||
case pointer + 4: audio_.set_length(index, value); break; \
|
||||
case pointer + 6: audio_.set_period(index, value); break; \
|
||||
case pointer + 8: audio_.set_volume(index, value); break; \
|
||||
case pointer + 10: audio_.set_data(index, value); break; \
|
||||
|
||||
Audio(0, 0x0a0);
|
||||
Audio(1, 0x0b0);
|
||||
@ -1098,29 +1024,25 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
|
||||
#undef Audio
|
||||
|
||||
// Copper.
|
||||
case Write(0x02e): copper_.set_control(cycle.value16()); break; // COPCON
|
||||
case Write(0x080): copper_.set_pointer<0, 16>(cycle.value16()); break; // COP1LCH
|
||||
case Write(0x082): copper_.set_pointer<0, 0>(cycle.value16()); break; // COP1LCL
|
||||
case Write(0x084): copper_.set_pointer<1, 16>(cycle.value16()); break; // COP2LCH
|
||||
case Write(0x086): copper_.set_pointer<1, 0>(cycle.value16()); break; // COP2LCL
|
||||
case Write(0x088): case Read(0x088):
|
||||
copper_.reload<0>();
|
||||
break;
|
||||
case Write(0x08a): case Read(0x08a):
|
||||
copper_.reload<1>();
|
||||
break;
|
||||
case Write(0x08c):
|
||||
LOG("TODO: coprocessor instruction fetch identity " << PADHEX(4) << cycle.value16());
|
||||
case 0x02e: copper_.set_control(value); break; // COPCON
|
||||
case 0x080: copper_.set_pointer<0, 16>(value); break; // COP1LCH
|
||||
case 0x082: copper_.set_pointer<0, 0>(value); break; // COP1LCL
|
||||
case 0x084: copper_.set_pointer<1, 16>(value); break; // COP2LCH
|
||||
case 0x086: copper_.set_pointer<1, 0>(value); break; // COP2LCL
|
||||
case 0x088: copper_.reload<0>(); break;
|
||||
case 0x08a: copper_.reload<1>(); break;
|
||||
case 0x08c:
|
||||
LOG("TODO: coprocessor instruction fetch identity " << PADHEX(4) << value);
|
||||
break;
|
||||
|
||||
// Sprites.
|
||||
#define Sprite(index, pointer, position) \
|
||||
case Write(pointer + 0): sprites_[index].set_pointer<0, 16>(cycle.value16()); break; \
|
||||
case Write(pointer + 2): sprites_[index].set_pointer<0, 0>(cycle.value16()); break; \
|
||||
case Write(position + 0): sprites_[index].set_start_position(cycle.value16()); break; \
|
||||
case Write(position + 2): sprites_[index].set_stop_and_control(cycle.value16()); break; \
|
||||
case Write(position + 4): sprites_[index].set_image_data(0, cycle.value16()); break; \
|
||||
case Write(position + 6): sprites_[index].set_image_data(1, cycle.value16()); break;
|
||||
case pointer + 0: sprites_[index].set_pointer<0, 16>(value); break; \
|
||||
case pointer + 2: sprites_[index].set_pointer<0, 0>(value); break; \
|
||||
case position + 0: sprites_[index].set_start_position(value); break; \
|
||||
case position + 2: sprites_[index].set_stop_and_control(value); break; \
|
||||
case position + 4: sprites_[index].set_image_data(0, value); break; \
|
||||
case position + 6: sprites_[index].set_image_data(1, value); break;
|
||||
|
||||
Sprite(0, 0x120, 0x140);
|
||||
Sprite(1, 0x124, 0x148);
|
||||
@ -1134,19 +1056,15 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
|
||||
#undef Sprite
|
||||
|
||||
// Colour palette.
|
||||
case Write(0x180): case Write(0x182): case Write(0x184): case Write(0x186):
|
||||
case Write(0x188): case Write(0x18a): case Write(0x18c): case Write(0x18e):
|
||||
case Write(0x190): case Write(0x192): case Write(0x194): case Write(0x196):
|
||||
case Write(0x198): case Write(0x19a): case Write(0x19c): case Write(0x19e):
|
||||
case Write(0x1a0): case Write(0x1a2): case Write(0x1a4): case Write(0x1a6):
|
||||
case Write(0x1a8): case Write(0x1aa): case Write(0x1ac): case Write(0x1ae):
|
||||
case Write(0x1b0): case Write(0x1b2): case Write(0x1b4): case Write(0x1b6):
|
||||
case Write(0x1b8): case Write(0x1ba): case Write(0x1bc): case Write(0x1be): {
|
||||
case 0x180: case 0x182: case 0x184: case 0x186: case 0x188: case 0x18a: case 0x18c: case 0x18e:
|
||||
case 0x190: case 0x192: case 0x194: case 0x196: case 0x198: case 0x19a: case 0x19c: case 0x19e:
|
||||
case 0x1a0: case 0x1a2: case 0x1a4: case 0x1a6: case 0x1a8: case 0x1aa: case 0x1ac: case 0x1ae:
|
||||
case 0x1b0: case 0x1b2: case 0x1b4: case 0x1b6: case 0x1b8: case 0x1ba: case 0x1bc: case 0x1be: {
|
||||
// Store once in regular, linear order.
|
||||
const auto entry_address = (register_address - 0x180) >> 1;
|
||||
const auto entry_address = (address - 0x180) >> 1;
|
||||
uint8_t *const entry = reinterpret_cast<uint8_t *>(&palette_[entry_address]);
|
||||
entry[0] = cycle.value8_high();
|
||||
entry[1] = cycle.value8_low();
|
||||
entry[0] = value >> 8;
|
||||
entry[1] = value & 0xff;
|
||||
|
||||
// Also store in bit-swizzled order. In this array,
|
||||
// instead of being indexed as [b4 b3 b2 b1 b0], index
|
||||
@ -1154,8 +1072,8 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
|
||||
// 32 colours, stored as half-bright.
|
||||
const auto swizzled_address = bitplane_swizzle(entry_address & 0x1f);
|
||||
uint8_t *const swizzled_entry = reinterpret_cast<uint8_t *>(&swizzled_palette_[swizzled_address]);
|
||||
swizzled_entry[0] = cycle.value8_high();
|
||||
swizzled_entry[1] = cycle.value8_low();
|
||||
swizzled_entry[0] = value >> 8;
|
||||
swizzled_entry[1] = value & 0xff;
|
||||
|
||||
swizzled_entry[64] = (swizzled_entry[0] >> 1) & 0x77;
|
||||
swizzled_entry[65] = (swizzled_entry[1] >> 1) & 0x77;
|
||||
@ -1163,12 +1081,70 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
|
||||
}
|
||||
|
||||
#undef ApplySetClear
|
||||
|
||||
#undef Write
|
||||
#undef Read
|
||||
#undef RW
|
||||
}
|
||||
|
||||
uint16_t Chipset::read(uint32_t address) {
|
||||
switch(address) {
|
||||
default:
|
||||
// If there was nothing to read, perform a write.
|
||||
// TODO: Rather than 0xffff, should be whatever is left on the bus, vapour-lock style.
|
||||
write(address, 0xffff);
|
||||
return 0xffff;
|
||||
|
||||
// Raster position.
|
||||
case 0x004: { // VPOSR; b15 = LOF, b0 = b8 of y position.
|
||||
const uint16_t position = uint16_t(y_ >> 8);
|
||||
return
|
||||
position |
|
||||
(is_long_field_ ? 0x8000 : 0x0000);
|
||||
|
||||
// b8–b14 should be:
|
||||
// 00 for PAL Agnus or fat Agnus
|
||||
// 10 for NTSC Agnus or fat Agnus
|
||||
// 20 for PAL high-res
|
||||
// 30 for NTSC high-res
|
||||
}
|
||||
case 0x006: { // VHPOSR; b0–b7 = horizontal; b8–b15 = low bits of vertical position.
|
||||
const uint16_t position = uint16_t(((line_cycle_ >> 1) & 0x00ff) | (y_ << 8));
|
||||
return position;
|
||||
}
|
||||
|
||||
case 0x00e: { // CLXDAT
|
||||
const uint16_t result = collisions_;
|
||||
collisions_ = 0;
|
||||
return result;
|
||||
};
|
||||
|
||||
// Joystick/mouse input.
|
||||
case 0x00a: return mouse_.get_position(); // JOY0DAT
|
||||
case 0x00c: return joystick(0).get_position(); // JOY1DAT
|
||||
|
||||
case 0x016: // POTGOR / POTINP
|
||||
// LOG("TODO: pot port read");
|
||||
return 0xff00;
|
||||
|
||||
// Disk DMA and control.
|
||||
case 0x010: // ADKCONR
|
||||
LOG("Read disk control");
|
||||
return paula_disk_control_;
|
||||
case 0x01a: // DSKBYTR
|
||||
LOG("TODO: disk status");
|
||||
assert(false); // Not yet implemented.
|
||||
return 0xffff;
|
||||
|
||||
// Serial port.
|
||||
case 0x018: // SERDATR
|
||||
LOG("TODO: serial data and status");
|
||||
return 0x3000; // i.e. transmit buffer empty.
|
||||
|
||||
// DMA management.
|
||||
case 0x002: return dma_control_ | blitter_.get_status(); // DMACONR
|
||||
|
||||
// Interrupts.
|
||||
case 0x01c: return interrupt_enable_; // INTENAR
|
||||
case 0x01e: return interrupt_requests_; // INTREQR
|
||||
}
|
||||
}
|
||||
|
||||
// MARK: - CRT connection.
|
||||
|
||||
|
||||
@ -107,6 +107,10 @@ class Chipset: private ClockingHint::Observer {
|
||||
private:
|
||||
friend class DMADeviceBase;
|
||||
|
||||
// MARK: - Register read/write functions.
|
||||
uint16_t read(uint32_t address);
|
||||
void write(uint32_t address, uint16_t value);
|
||||
|
||||
// MARK: - E Clock and keyboard dividers.
|
||||
|
||||
HalfCycles cia_divider_;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user