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Strongly type BusOperation.

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This commit is contained in:
Thomas Harte 2025-01-07 22:48:17 -05:00
parent 5b8a005f41
commit f195dc313d
2 changed files with 61 additions and 24 deletions
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8
Processors/6502Esque/6502Esque.hpp
View File

@ -64,7 +64,7 @@ enum Flag: uint8_t {
Bus handlers will be given the task of performing bus operations, allowing them to provide whatever interface they like
between a 6502-esque chip and the rest of the system. @c BusOperation lists the types of bus operation that may be requested.
*/
enum BusOperation {
enum class BusOperation {
/// 6502: indicates that a read was signalled.
/// 65816: indicates that a read was signalled with VDA.
Read,
@ -99,17 +99,17 @@ enum BusOperation {
/*!
For a machine watching only the RWB line, evaluates to @c true if the operation should be treated as a read; @c false otherwise.
*/
#define isReadOperation(v) (v <= CPU::MOS6502Esque::InternalOperationRead)
#define isReadOperation(v) (v <= CPU::MOS6502Esque::BusOperation::InternalOperationRead)
/*!
For a machine watching only the RWB line, evaluates to @c true if the operation is any sort of write; @c false otherwise.
*/
#define isWriteOperation(v) (v >= CPU::MOS6502Esque::Write)
#define isWriteOperation(v) (v >= CPU::MOS6502Esque::BusOperation::Write)
/*!
Evaluates to @c true if the operation actually expects a response; @c false otherwise.
*/
#define isAccessOperation(v) ((v <= CPU::MOS6502Esque::ReadVector) || (v == CPU::MOS6502Esque::Write))
#define isAccessOperation(v) ((v <= CPU::MOS6502Esque::BusOperation::ReadVector) || (v == CPU::MOS6502Esque::BusOperation::Write))
/*!
A class providing empty implementations of the methods a 6502 uses to access the bus. To wire the 6502 to a bus,

77
Processors/65816/Implementation/65816Implementation.hpp
View File

@ -13,8 +13,8 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
bus_value_ = value; \
bus_operation_ = operation
#define read(address, value) perform_bus(address, value, MOS6502Esque::Read)
#define write(address, value) perform_bus(address, value, MOS6502Esque::Write)
#define read(address, value) perform_bus(address, value, MOS6502Esque::BusOperation::Read)
#define write(address, value) perform_bus(address, value, MOS6502Esque::BusOperation::Write)
#define m_flag() registers_.mx_flags[0]
#define x_flag() registers_.mx_flags[1]
@ -85,29 +85,45 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
//
case CycleFetchOpcode:
perform_bus(registers_.pc | registers_.program_bank, instruction_buffer_.next_input(), MOS6502Esque::ReadOpcode);
perform_bus(
registers_.pc | registers_.program_bank,
instruction_buffer_.next_input(),
MOS6502Esque::BusOperation::ReadOpcode
);
++registers_.pc;
break;
case CycleFetchIncrementPC:
perform_bus(registers_.pc | registers_.program_bank, instruction_buffer_.next_input(), MOS6502Esque::ReadProgram);
perform_bus(
registers_.pc | registers_.program_bank,
instruction_buffer_.next_input(),
MOS6502Esque::BusOperation::ReadProgram
);
++registers_.pc;
break;
case CycleFetchPC:
perform_bus(registers_.pc | registers_.program_bank, instruction_buffer_.next_input(), MOS6502Esque::ReadProgram);
perform_bus(
registers_.pc | registers_.program_bank,
instruction_buffer_.next_input(),
MOS6502Esque::BusOperation::ReadProgram
);
break;
case CycleFetchPCThrowaway:
perform_bus(registers_.pc | registers_.program_bank, &bus_throwaway_, MOS6502Esque::InternalOperationRead);
perform_bus(
registers_.pc | registers_.program_bank,
&bus_throwaway_,
MOS6502Esque::BusOperation::InternalOperationRead
);
break;
case CycleFetchPreviousPCThrowaway:
perform_bus(((registers_.pc - 1) & 0xffff) | registers_.program_bank, &bus_throwaway_, MOS6502Esque::InternalOperationRead);
perform_bus(((registers_.pc - 1) & 0xffff) | registers_.program_bank, &bus_throwaway_, MOS6502Esque::BusOperation::InternalOperationRead);
break;
case CycleFetchPreviousThrowaway:
perform_bus(bus_address_, &bus_throwaway_, MOS6502Esque::InternalOperationRead);
perform_bus(bus_address_, &bus_throwaway_, MOS6502Esque::BusOperation::InternalOperationRead);
break;
//
@ -124,17 +140,29 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
case CycleStoreOrFetchDataThrowaway:
if(registers_.emulation_flag) {
perform_bus(data_address_, data_buffer_.preview_output(), MOS6502Esque::InternalOperationWrite);
perform_bus(
data_address_,
data_buffer_.preview_output(),
MOS6502Esque::BusOperation::InternalOperationWrite
);
break;
}
[[fallthrough]];
case CycleFetchDataThrowaway:
perform_bus(data_address_, &bus_throwaway_, MOS6502Esque::InternalOperationRead);
perform_bus(
data_address_,
&bus_throwaway_,
MOS6502Esque::BusOperation::InternalOperationRead
);
break;
case CycleFetchIncorrectDataAddress:
perform_bus(incorrect_data_address_, &bus_throwaway_, MOS6502Esque::InternalOperationRead);
perform_bus(
incorrect_data_address_,
&bus_throwaway_,
MOS6502Esque::BusOperation::InternalOperationRead
);
break;
case CycleFetchIncrementData:
@ -143,11 +171,11 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
break;
case CycleFetchVector:
perform_bus(data_address_, data_buffer_.next_input(), MOS6502Esque::ReadVector);
perform_bus(data_address_, data_buffer_.next_input(), MOS6502Esque::BusOperation::ReadVector);
break;
case CycleFetchIncrementVector:
perform_bus(data_address_, data_buffer_.next_input(), MOS6502Esque::ReadVector);
perform_bus(data_address_, data_buffer_.next_input(), MOS6502Esque::BusOperation::ReadVector);
increment_data_address();
break;
@ -170,7 +198,11 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
break;
case CycleFetchBlockY:
perform_bus(((instruction_buffer_.value & 0x00ff) << 16) | registers_.y.full, &bus_throwaway_, MOS6502Esque::InternalOperationRead);
perform_bus(
((instruction_buffer_.value & 0x00ff) << 16) | registers_.y.full,
&bus_throwaway_,
MOS6502Esque::BusOperation::InternalOperationRead
);
break;
case CycleStoreBlockY:
@ -190,14 +222,14 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
bus_operation_ = operation;
case CyclePush:
stack_access(data_buffer_.next_output_descending(), MOS6502Esque::Write);
stack_access(data_buffer_.next_output_descending(), MOS6502Esque::BusOperation::Write);
--registers_.s.full;
break;
case CyclePushNotEmulation:
bus_address_ = registers_.s.full;
bus_value_ = data_buffer_.next_output_descending();
bus_operation_ = MOS6502Esque::Write;
bus_operation_ = MOS6502Esque::BusOperation::Write;
--registers_.s.full;
break;
@ -209,18 +241,18 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
case CyclePull:
++registers_.s.full;
stack_access(data_buffer_.next_input(), MOS6502Esque::Read);
stack_access(data_buffer_.next_input(), MOS6502Esque::BusOperation::Read);
break;
case CyclePullNotEmulation:
++registers_.s.full;
bus_address_ = registers_.s.full;
bus_value_ = data_buffer_.next_input();
bus_operation_ = MOS6502Esque::Read;
bus_operation_ = MOS6502Esque::BusOperation::Read;
break;
case CycleAccessStack:
stack_access(&bus_throwaway_, MOS6502Esque::InternalOperationRead);
stack_access(&bus_throwaway_, MOS6502Esque::BusOperation::InternalOperationRead);
break;
#undef stack_access
@ -242,7 +274,12 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
continue;
} else {
--next_op_;
perform_bus(0xffffff, &bus_throwaway_, (required_exceptions_ & IRQ) ? MOS6502Esque::Ready : MOS6502Esque::None);
perform_bus(
0xffffff,
&bus_throwaway_,
(required_exceptions_ & IRQ) ?
MOS6502Esque::BusOperation::Ready : MOS6502Esque::BusOperation::None
);
}
break;