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mirror of https://github.com/TomHarte/CLK.git synced 2024-11-26 23:52:26 +00:00

Consolidate repetition in CLR.

This commit is contained in:
Thomas Harte 2022-10-11 11:22:34 -04:00
parent 77bc60bf86
commit f3f23f90a3

View File

@ -88,10 +88,14 @@ static void add_sub(IntT source, IntT &destination, Status &status) {
destination = result; destination = result;
} }
/// @returns the name of the bit to be used as a mask for BCLR, BCHG, BSET or BTST for
/// @c instruction given @c source.
inline uint32_t mask_bit(const Preinstruction &instruction, uint32_t source) { inline uint32_t mask_bit(const Preinstruction &instruction, uint32_t source) {
return source & (instruction.mode<1>() == AddressingMode::DataRegisterDirect ? 31 : 7); return source & (instruction.mode<1>() == AddressingMode::DataRegisterDirect ? 31 : 7);
} }
/// Performs a BCLR, BCHG or BSET as specified by @c operation and described by @c instruction, @c source and @c destination, updating @c destination and @c status.
/// Also makes an appropriate notification to the @c flow_controller.
template <Operation operation, typename FlowController> template <Operation operation, typename FlowController>
void bit_manipulate(const Preinstruction &instruction, uint32_t source, uint32_t &destination, Status &status, FlowController &flow_controller) { void bit_manipulate(const Preinstruction &instruction, uint32_t source, uint32_t &destination, Status &status, FlowController &flow_controller) {
static_assert(operation == Operation::BCLR || operation == Operation::BCHG || operation == Operation::BSET); static_assert(operation == Operation::BCLR || operation == Operation::BCHG || operation == Operation::BSET);
@ -106,6 +110,12 @@ void bit_manipulate(const Preinstruction &instruction, uint32_t source, uint32_t
flow_controller.did_bit_op(int(bit)); flow_controller.did_bit_op(int(bit));
} }
/// Sets @c destination to 0, clears the overflow, carry and negative flags, sets the zero flag.
template <typename IntT> void clear(IntT &destination, Status &status) {
destination = 0;
status.negative_flag = status.overflow_flag = status.carry_flag = status.zero_result = 0;
}
} }
template < template <
@ -229,20 +239,9 @@ template <
CLRs: store 0 to the destination, set the zero flag, and clear CLRs: store 0 to the destination, set the zero flag, and clear
negative, overflow and carry. negative, overflow and carry.
*/ */
case Operation::CLRb: case Operation::CLRb: Primitive::clear(src.b, status); break;
src.b = 0; case Operation::CLRw: Primitive::clear(src.w, status); break;
status.negative_flag = status.overflow_flag = status.carry_flag = status.zero_result = 0; case Operation::CLRl: Primitive::clear(src.l, status); break;
break;
case Operation::CLRw:
src.w = 0;
status.negative_flag = status.overflow_flag = status.carry_flag = status.zero_result = 0;
break;
case Operation::CLRl:
src.l = 0;
status.negative_flag = status.overflow_flag = status.carry_flag = status.zero_result = 0;
break;
/* /*
CMP.b, CMP.l and CMP.w: sets the condition flags (other than extend) based on a subtraction CMP.b, CMP.l and CMP.w: sets the condition flags (other than extend) based on a subtraction